Features• Complete DTMF Receiver• Low power consumption• Internal gain setting amplifier• Adjustable guard time• Central office quality• Power-down mode• Inhibit mode• Backward compatible withMT8870C/MT8870C-1Applications• Receiver system for British Telecom (BT) orCEPT Spec (MT8870D-1)• Paging systems• Repeater systems/mobile radio• Credit card systems• Remote control• Personal computers• Telephone answering machine
上传时间： 2013-11-20
上传用户：mpquest
根据看门狗电路的原理，设计出简单适用、性能可靠的1TrL型看门狗电路以及价格低廉、性能可靠的微功耗CMOS型看门狗电路，同时还介绍了常用的uP监视器O型看门狗电路。关键词：看门狗电路；1TrL型；CMOS型Abstract：In accordance with the principle of WDT (Watch Dog Timer 1circuit，design a，IT．L type WTD circuit，it is a dimple an d applicable an d reliable on performanceo Design a CMOS type WTD circuit，it is low prices and mini-power consumption。Also the article describes a common uP type WTD circuit。Key word：WDT circuit；TFL type；CMOS typ e
上传时间： 2013-11-05
上传用户：685
The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self−timed write cycle. Additionally, the CAT28LV64 features hardware and software write protection.
上传时间： 2013-11-16
上传用户：浩子GG
MC9S08QG8英文资料 The MC9S08QG8 is the newest member of the Freescale 8-bit family of highly integratedmicrocontrollers, based on the high-performance yet low power HCS08 core. The MC9S08QG8is an excellent solution for power-sensitive applications with extended battery life and maximum performance down to 1.8VDC.
上传时间： 2014-12-28
上传用户：dxxx
1.The C Programming Language is a powerful, flexible andpotentially portable high-level programming language. 2.The C language may be used successfully to create a programfor an 8-bit MCU, but to produce the most efficient machinecode, the programmer must carefully construct the C Languageprogram.3.The programmer must not only create an efficient high leveldesign, but also pay attention to the detailed implementation.
上传时间： 2013-12-27
上传用户：huanglang
汇编器在微处理器的验证和应用中举足轻重，如何设计通用的汇编器一直是研究的热点之一。本文提出了一种开放式的汇编器系统设计思想，在汇编语言与机器语言间插入中间代码CMDL（code mapping description language）语言，打破汇编语言与机器语言的直接映射关系，由此建立起一套描述汇编语言与机器语言的开放式映射体系。基于此开放式映射体系开发了一套汇编器系统，具有较高层次上的通用性和可移植性。【关键词】指令集，CMDL，汇编器，开放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【关键词】instruction set, symbol table, assembler, lexical analysis, retargetability
上传时间： 2013-10-10
上传用户：meiguiweishi
1、 支持USB 1.1通讯协议；2、 支持高速（Full Speed、12Mbps ）和低速（Low Speed、1.5Mbps ）传输；3、 6MHz晶体，锁相环PLL振荡器提供高速、低速所需时钟源；4、 支持3个端口（endpoint），可独立编程为IN 或 OUT端口。5、 PS/2：支持PS/2协议（eg.鼠标），与USB复用。
上传时间： 2013-11-03
上传用户：hbsunhui
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上传时间： 2013-10-10
上传用户：inwins
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
标签： 4channel multiple 9544A 9544
上传时间： 2014-12-28
上传用户：潜水的三贡
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上传时间： 2014-11-22
上传用户：xcy122677
