采用VHDL硬件描述语言设计，包含加法器，乘法器等以及寄存器的详细设计思路和设计源码
标签： SOC课程设计
上传时间： 2015-04-16
上传用户：kaixinyixiaxia
SOPC开发快速入门教程中文版，以非常详细的实例来让初学者了解基于QII和NII的FPGA/SOC的开发的基本流程，目的是为了让初学者尽快上手。
标签： FPGA SOC
上传时间： 2015-10-08
上传用户：shzweh1234
锂电池离线辨识方法，论文，在确定二阶RC 等效电路模型的基础上, 采用渐衰记忆的递推最小二乘算法和扩展卡尔曼滤波算法对模型参数与 SOC 在线联合估算。经过实验与仿真验证,
上传时间： 2016-01-21
上传用户：zxljj3825
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio™ suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: Clocking System Digital Audio Interface Analog Audio Interface Power supply Clocks, digital PLL I2C control interface 8051 MCUcontroller Audio DSP – digital audio processing 特性 Digital Audio Processor Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio™ Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48)
上传时间： 2016-05-06
上传用户：fagong
在锂电池的估算中运用了卡尔曼滤波进行估算
上传时间： 2017-05-10
上传用户：到底奚不奚
为了确定拟合系数运用最下二乘法进行拟合。。
标签： SOC
上传时间： 2017-05-10
上传用户：到底奚不奚
EGO1 是依元素科技基于 Xilinx Artix-7 FPGA 研发的便携式数模混合基础教 学平台。EGO1 配备的 FPGA (XC7A35T-1CSG324C)具有大容量高性能等特点， 能实现较复杂的数字逻辑设计；在 FPGA 内可以构建 MicroBlaze 处理器系统， 可进行 SoC 设计。该平台拥有丰富的外设，以及灵活的通用扩展接口。
上传时间： 2017-10-14
上传用户：wlwl
1/4-inch, 5-Megapixel SOC Image Sensor Optimized for High-Volume Mobile Markets
上传时间： 2019-09-29
上传用户：wsgq2019
用 verilog HDL 语言搭建一个以 ARM Cortex-M0 为处理器核的嵌入式SOC系统,系统包含以下几个部分： (1)ARM Cortex-M0核 (2)AHB总线译码器 (3)AHB总线从设备多路复用器 (4)片上存储器外设 (5)LED外设 (6)七段数码管 (7)定时器 (8)UART
上传时间： 2020-03-21
上传用户：wssss
为克服目前负载识别终端的低准确率、高复杂度、高硬件成本等弊端，该文设计了一 种基于SoC芯片RN8213B的微型化、多功能的智能电表。 阐述和应用了相似度负载识别算 法， 应用了两光耦485通信和开关电源等技术
上传时间： 2021-09-19
上传用户：13349833106
