C8051F340/1/2/3/4/5/6/7 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection
标签： System-on-a-Chip mixed-signal Highlighted integrated
上传时间： 2014-01-01
上传用户：牧羊人8920
example of a 7 pulse multiple pulse width modulation with tow=0.8
标签： pulse modulation multiple example
上传时间： 2017-08-18
上传用户：13517191407
ICKTEK-VC5509-A 实验3.7 自启动实验
上传时间： 2017-09-02
上传用户：wcl168881111111
Its a encryption tool for delphi 7. Its can encrypt with blowfish, md5, base64...
标签： encryption Its blowfish encrypt
上传时间： 2014-01-20
上传用户：大融融rr
Nexus is a Memory Manager for Delphi 7. Its usefull for all application what is work with large amount of variable. Help for avoid the memory leaks.
标签： application for Manager usefull
上传时间： 2017-09-03
上传用户：ynwbosss
This is a part of exercises with book Stephan Prata "School of programing" ex.7.1-7.9
标签： programing exercises Stephan School
上传时间： 2017-09-12
上传用户：wanqunsheng
adder 4 + 4 bits, for use with a Altera, and 2 displays 7 segments
标签： displays segments Altera adder
上传时间： 2017-09-20
上传用户：luke5347
cadence 15.7安装步骤及方法安装步骤： 1、 证书生成 a、双击Crack->keygen.exe， b、HO
上传时间： 2013-07-26
上传用户：xoxoliguozhi
A/D 型单片机使用说明书/手册 第一部份 单片机概论.................................................................. 1第一章 硬件结构........................................................................................ 3简介..............................................................................................................3特性..............................................................................................................4技术特性..............................................................................................4内核特性..............................................................................................4周边特性..............................................................................................5选择表..........................................................................................................5系统框线图..................................................................................................6引脚分配......................................................................................................7引脚说明......................................................................................................8极限参数....................................................................................................12直流电气特性............................................................................................13交流电气特性............................................................................................14系统结构....................................................................................................15时序和流水线结构(Pipelining) .........................................................15程序计数器........................................................................................17堆栈....................................................................................................19算术及逻辑单元 – ALU...................................................................20程序存储器................................................................................................21结构....................................................................................................21特殊向量............................................................................................22查表....................................................................................................23查表程序范例....................................................................................23数据存储器................................................................................................25结构....................................................................................................25通用数据存储器................................................................................26专用数据存储器................................................................................27
上传时间： 2014-12-27
上传用户：youlongjian0
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-19
上传用户：yyyyyyyyyy
