一个VEILOG hDl程序，可以直接应用，
上传时间： 2014-01-21
上传用户：chongcongying
1024点fft verilog hDl
上传时间： 2013-12-25
上传用户：redmoons
Verilog hDl程序设计教程，非常实用，对学习Verilog非常有用。
上传时间： 2014-01-06
上传用户：妄想演绎师
verilog hDl coding DDR sdram control for fpga
标签： verilog control coding sdram
上传时间： 2013-12-17
上传用户：wangchong
利用verlilog hDl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！
上传时间： 2015-12-10
上传用户：erkuizhang
该代码中有不少关于学习verilog hDl的例子,对初学者有帮助
上传时间： 2013-12-19
上传用户：asdkin
Verilog hDl课件，有常见问题说明
上传时间： 2013-12-21
上传用户：sdq_123
Verilog hDl的标准，比较详细的语法说明
上传时间： 2015-12-15
上传用户：xsnjzljj
As the Hardware Description Language (hDl) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one hDl to another.
标签： Description enhancement activities the
上传时间： 2015-12-15
上传用户：sunjet
Testbenches have become an integral part of the design process, enabling you to verify that your hDl model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
标签： Testbenches enabling integral process
上传时间： 2014-01-25
上传用户：ynzfm
