java applet code for generating RSA key pair
标签： generating applet java code
上传时间： 2014-08-15
上传用户：manking0408
For generating wind speed model in ARMA
标签： generating speed model ARMA
上传时间： 2017-06-25
上传用户：
XML parser with DOM. Helps on parsing and generating a directory structure
标签： generating directory structure parsing
上传时间： 2014-12-06
上传用户：ywqaxiwang
递归法生成2D迷宫,Recursive method generating 2D maze
标签： generating Recursive method maze
上传时间： 2017-07-09
上传用户：libinxny
guitar tunner... useful for generating varius tunes
标签： generating guitar tunner useful
上传时间： 2013-12-21
上传用户：181992417
generating histogram
标签： generating histogram
上传时间： 2017-07-20
上传用户：BIBI
generating Jasper Reports with Java
标签： generating Reports Jasper Java
上传时间： 2014-01-20
上传用户：牧羊人8920
·详细说明：双音多频（DTMF）信号发生器的使用源程序，vc 编写，与《双音多频（DTMF）接收器的使用源程序》联合用- The double sound multi- frequencies (DTMF) the signal generating device use source program, the vc compilation, (DTMF) Receiver Use Source p
上传时间： 2013-07-23
上传用户：tianjinfan
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上传时间： 2013-10-25
上传用户：banyou
The purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-up DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-up DC-DC converter (capable of generating up to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input supply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).
上传时间： 2014-12-23
上传用户：781354052
