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  • Electromagnetic+Transients+in+Power+Cables

    For more than a century, overhead lines have been the most commonly used technology for transmitting electrical energy at all voltage levels, especially on the highest levels. However, in recent years, an increase in both the number and length of HVAC cables in the transmission networks of different countries like Denmark, Japan or United Kingdom has been observed. At the same time, the construction of offshore wind farms, which are typically connected to the shore through HVAC cables, increased exponentially.

    标签: Electromagnetic Transients Cables Power in

    上传时间: 2020-06-07

    上传用户:shancjb

  • lagr.m

    function y=lagr(x0,y0,x) %x0,y0为节点 %x是插值点 n=length(x0); m=length(x); for i=1:m z=x(i); s=0.0; for k=1:n p=1.0; for j=1:n if j~=k p=p*(z-x0(j))/(x0(k)-x0(j)); end end s=p*y0(k)+s; end y(i)=s; end

    标签: lagr

    上传时间: 2020-06-09

    上传用户:shiyc2020

  • DDR4标准 JESD79_4

    1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34

    标签: DDR4

    上传时间: 2022-01-09

    上传用户:

  • 电流检测电路中运算放大器与ADC的设计

    电学中的测量技术涉及范围非常广,电流测量在电学计量中占有非常重要的位置。如何精确地进行电流测量是精密测量的一大难题。传统的电流检测电路多采用运算放大芯片与片外电流检测电路相结合的方式,电路集成度很低,需要较多的接口和资源才能完成对电路的检测。本文把所有电路部分都集成在一块芯片上,包括检测电阻,运算放大器电路及模拟转数字转换电路,从而在电路内部可以进行电流检测,使电路更好的集成化。前置电路使用二级共源共栅结构的运算放大器,减小沟道长度调制效应造成的电流误差。10位SAR ADC中采用电容驱动能力强的传输门保证了模数转化器的有效精度。比较器模块采用再生锁存器与迟滞比较器作为基础单元组合解决精密测量的问题。本设计可以作为嵌入芯片内的一小部分而检测芯片中的微小电流1mA~100mA,工作电压在1.8v左右,电流检测精度预期达到10uA的需求。The measurement technology in electricity involves a wide range,and current measurement plays a very important position in electrical measurement.How to accurately measure current is a big problem in precision measurement. The traditional current detecting circuit adopts the combination of the operational amplifier chip and theoff-chip current detecting circuit, The circuit integration is very low, and more interfaces and resources are needed tocomplete the circuit detection.This topic integrates all the circuit parts into one chip, including detection resistance, operational amplifier circuit andanalog to digital conversion circuit. Highly integrated circuit makes the external resources on the chip more intensive,so that current detection can be carried out inside the circuit, so that the circuit can be better integrated. Thefront-end circuit of this project uses two-stage cascade operational amplifier and cascade tube to reduce the currenterror caused by channel length modulation effect. In 10-bit SAR ADC, the transmission gate with strong capacitivedriving ability ensures the effective accuracy of the analog-to-digital converter. Comparator module uses regenerativelatch and hysteresis comparator as basic unit to solve the difficult problem of precision measurement. This topic can beused as a small part of the embedded chip to detect the micro-current in the chip 1 mA~100 mA, the working voltageis about 1.8v, and the current detection accuracy is expected to reach the requirement of 10 uA.

    标签: 电流检测 电路 运算放大器 adc

    上传时间: 2022-04-03

    上传用户:

  • IGBT图解

    le flows through MOS channel while Ih flows across PNP transistor Ih= a/(1-a) le, IE-le+lh=1/(1-a)' le Since IGBT has a long base PNP, a is mainly determined by ar si0 2ar= 1/cosh(1/La), La: ambipolar diff length a-0.5 (typical value)p MOSFET channel current (saturation), le=U"Cox"W(2"Lch)"(Vc-Vth)le Thus, saturated collector current Ic, sat=1/(1-a)"le=-1/(1-a)"UCox"W/(2Lch)"(Vo-Vth)2Also, transconductance gm, gm= 1/(1-a)"u' Cox W/Lch*(Vo-Vth)Turn-On1. Inversion layer is formed when Vge>Vth2. Apply positive collector bias, +Vce3. Electrons flow from N+ emitter to N-drift layer providing the base current for the PNP transistor4. Since J1 is forward blased, hole carriers are injected from the collector (acts as an emitter).5. Injected hole carriers exceed the doping level of N-drift region (conductivity modulation). Turn-Off1. Remove gate bias (discharge gate)2. Cut off electron current (base current, le, of pnp transistor)

    标签: igbt

    上传时间: 2022-06-20

    上传用户:wangshoupeng199

  • wireshark抓包分析TCP和UDP

    1,使用wireshark获取完整的UDP报文打开wireshark,设置监听网卡后,使用google chrome浏览器访问我腾讯微博的i http://p.t.qq.com/welcomeback.php?lv=1#!/ist/qqfriends/5/?pgv_ref-im.perinfo.pe rinfo.icon?ptlang-2052&pgv-ref-im.perinfo.perinfo.icon,抓得的UDP报文如图1所示。分析以上的报文内容,UDP作为一种面向无连接服务的运输协议,其报文格式相当简单。第一行中,Source port:64318是源端口号。第二行中,Destination port:53是目的端口号。第三行中,Length:34表示UDP报文段的长度为34字节。第四行中,Checksum之后的数表示检验和。这里0x表示计算机中16进制数的开始符,其后的4f0e表示16进制表示的检验和,把它们换成二进制表示为:0100 1111 0000 1110.从wireshark的抓包数据看出,我抓到的UDP协议多数被应用层的DNS协议应用。当一台主机中的DNS应用程序想要进行一次查询时,它构成了一个DNS查询报文并将其交给UDP,UDP无须执行任何实体握手过程,主机端的UDP为此报文添加首部字段,并将其发出。

    标签: wireshark tcp udp

    上传时间: 2022-06-20

    上传用户:

  • VITA46-48-42 技术资料

    VITA 46 Highlights Retain standard 6U and 3U form-factors Height, depth, pitch, front panel arrangements, conduction-cooled interfaces, etc.Support standard-length PMC and XMC modules· Support high-speed serial fabric on the backplane Tyco MultiGig RT2,7-row connector· Support VME and PCI interfaces for legacy compatibility· Provision for optical connectors as option· Support improved logistics Provide support for Line Replaceable Module(LRM) applications with ESD-protected connector Alignment and keying blocks

    标签: vita46

    上传时间: 2022-07-25

    上传用户: