The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time delay.
标签： autocorrelation objective generator projectis
上传时间： 2015-08-17
上传用户：ikemada
数字选台收音机 注意： （1）遥控发射芯片用TC9012/TC9243 经常用到的还有UPD6121和LC7461，它们的不同只处在于引导码的时间不同或者数据位的个数不同，接受原理基本一样。将本程序的相关位置修改就可以通用。 系统时钟22.1184MHZ，如果用其他的时钟请将delay.c文件中的定时器装载值修改一下 （2） 键盘检测在VFD程序中，16312可以驱动VFD，另外外部可接24个按键，并将按键值放到 其内部的存储中，使用时只须发命令读即可。 （3） 由于时间原因，只给出调幅波段的自动搜台功能，调频的自动搜台程序和调幅一样，自己写了。 （4）主要用在组合机和功放机上的收音头大部分以LC72171做锁象环，LA1823做高中频处理 和音频解调，但是有的数调收音头把锁象环和高频处理做在一起，典型的有TEA5757和TEA5756 TEA5757采用了一种所谓的自动调谐系统，在自动搜索时无须读中频，简化了程序。
上传时间： 2013-12-28
上传用户：gxmm
oid led8_test(void) { int i, j, k iic_init() for( ) { for(j=0 j<10 j++) { for(i=0 i<8 i++) { k = 9-(i+j)％10 iic_write(0x70, 0x10+i, f_szDigital[k]) } delay(1000) } } }
上传时间： 2013-12-19
上传用户：BOBOniu
一个简单的串口文件发送接受程序。可以调节发送延迟。里面的类可以应用在其他的环境下。A simple program that can send a file through a serial port. The delay and other parameters are changable.
标签： program through simple serial
上传时间： 2014-01-22
上传用户：zsjinju
This simple program help you to calculate parameters for a pid controller for first order systems wiith delay using different method: Ziegler Nichols,Cohen coon,IMC...
标签： controller parameters calculate for
上传时间： 2015-11-09
上传用户：yuanyuan123
Mobile phones are constantly decreasing in size, thereby complicating the acoustical functionality. Signal processing methods can be used to partially mitigate this problem. In this paper we suggest a method which uses multiple spectral subtraction functions and two microphones, introducing only a short signal delay.
标签： functionality complicating acoustical constantly
上传时间： 2015-11-15
上传用户：youth25
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
标签： Development Startix2 tailored Altera
上传时间： 2014-01-19
上传用户：chongcongying
The present paper deals with the problem of calculating mean delays in polling systems with either exhaustive or gated service. We develop a mean value analysis (MVA) to compute these delay figures. The merits of MVA are in its intrinsic simplicity and its intuitively appealing derivation. As a consequence, MVA may be applied, both in an exact and approximate manner, to a large variety of models.
标签： with calculating present polling
上传时间： 2014-11-17
上传用户：kelimu
This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
标签： block-by-block acquired example streams
上传时间： 2015-12-29
上传用户：bjgaofei
名称：read2543 功能：TLC2543驱动模块 输入参数：port通道号 输出参数：ad转换值 *************************************/ uint read2543(uchar port) { uint ad=0,i CLOCK=0 _CS=0 port<<=4 for(i=0 i<12 i++) { if(D_OUT) ad|=0x01 D_IN=(bit)(port&0x80) CLOCK=1 delay(3) CLOCK=0 delay(3) port<<=1 ad<<=1 } _CS=1 ad>>=1 return(ad) }
上传时间： 2016-01-21
上传用户：R50974
