微电脑型单相交流集合式电表（单相二线系统） 特点： 精确度0.25%满刻度±1位数 可同时量测与显示交流电压,電流,頻率,瓦特,(功率因數/視在功率) 交流電壓,電流,瓦特皆為真正有效值(TRMS) 交流電流,瓦特之小數點可任意設定 瓦特單位W或KW可任意設定 CT比可任意設定(1至999) 輸入與輸出絕緣耐压 2仟伏特/1分鐘( 突波測試強度4仟伏特(1.2x50us) 數位RS-485界面 (Optional) 主要规格： 精确度: 0.1% F.S.±1 digit (Frequency) 0.25% F.S.±1 digit(ACA,ACV,Watt,VA) 0.25% F.S. ±0.25o(Power Factor) (-.300~+.300) 输入负载: <0.2VA (Voltage) <0.2VA (Current) 最大过载能力: Current related input: 3 x rated continuous 10 x rated 30 sec. 25 x rated 3sec. 50 x rated 1sec. Voltage related input: maximum 2 x rated continuous 过载显示: "doFL" 显示值范围: 0~600.0V(Voltage) 0~999.9Hz(Frequency)(<20% for voltage input) 0~19999 digit adjustable(Current,Watt,VA) 取样时间: 2 cycles/sec. RS-485通讯位址: "01"-"FF" RS-485传输速度: 19200/9600/4800/2400 selective RS-485通信协议: Modbus RTU mode 温度系数: 100ppm/℃ (0-50℃) 显示幕: Red high efficiency LEDs high 10.16 mm(0.4") 参数设定方式: Touch switches 记忆型式: Non-volatile E²PROM memory 绝缘抗阻: >100Mohm with 500V DC 绝缘耐压能力: 2KVac/1 min. (input/output/power) 1600 Vdc (input/output) 突波测试: ANSI c37.90a/1974,DIN-IEC 255-4 impulse voltage 4KV(1.2x50us) 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上传时间： 2015-01-03
上传用户：几何公差
集合式直流电能表（小功率的） 特点： 精确度0.05%满刻度±1位数 可同时量测与显示/直流电压/电流/瓦特（千瓦）/瓦特小时（千瓦小时） 电压输入（DC0-99.99V/0-600.0V）自动变档功能 显示范围0-9999(电流/瓦特/千瓦),0至99999999(八位數瓦特小时)可任意规划 数位RS-485 界面 (Optional) 主要规格： 辅助电源消耗功率：＜0.35VA(DC12V/DC24V) ＜0.5VA（DC48V） ＜1.5VA（AC90-240V(50/60Hz)） 精确度: 0.05% F.S. ±1 digit (23 ±5℃) 输入范围：Auto range(DC0-99.99V/0-600.0V(DC voltage)) 输入抗阻：＞5MΩ（DC voltage） 取样时间：10 cycles/second(total) 过载显示: " doFL " 显示值范围: 0-9999 digit（DCA/W(KW)） 0-9999999.999 digit(WH/(KWH)) RS-485传输速度: 19200/9600/4800/2400 selective RS-485通讯位址: "01"-"FF"（0-255） RS-485通信协议: Modbus RTU mode 温度系数: 50ppm/℃ (0-50℃) 显示幕:Bight Red LEDs high 10.16 mm(0.4") 参数设定方式: Touch switches 记忆方式: Non-volatile E²PROM memory 绝缘耐压能力:2KVac/1min.(input/output)（RS-485(Isolating)） 1600 Vdc (input/output) （RS-485(Isolating)） 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上传时间： 2013-11-20
上传用户：s363994250
Full support for extended regular expressions (those with intersection and complement); Support for some kinds of cycles in grammar; DFA-based operation; Unicode support; C++ only, requires a modern compiler; Lexical analyzers can be configured to get symbols from any input class (built-in support for std::istream, std::wistream and FILE *); Designed to work with Whale, but can work standalone or interface to other parsers.
标签： intersection expressions complement for
上传时间： 2013-12-11
上传用户：zhanditian
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
标签： 8226 Programmable Compatible In-System
上传时间： 2015-06-27
上传用户：dianxin61
This example program shows how to configure PCA Module 4 as a watchdog timer. In this example, the watchdog is configured to overflow after 0xFF00 clock cycles.
标签： example configure watchdog program
上传时间： 2016-02-09
上传用户：bakdesec
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and used only durring TA_ISR. ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
标签： Toggle Description 5.1 Contmode
上传时间： 2014-01-04
上传用户：gut1234567
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
标签： Description Behavorial wb_master Filename
上传时间： 2014-07-11
上传用户：zhanditian
The algorith divides rows in to four equal groups. The rows are then used to from a distance graph which is then transformed into a matrix. girth of eight is maintained by avoiding six-cycles in the graph construction
标签： rows The algorith distance
上传时间： 2014-01-15
上传用户：kelimu
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
标签： Wishbone Supports includes Low-Pin
上传时间： 2014-12-20
上传用户：古谷仁美
Topics Practices: Programming and Numerical Methods Practice 1: Introduction to C Practice 2: cycles and functions First part cycles Part Two: Roles Practice 3 - Floating point arithmetic Practice 4 - Search for roots of functions Practice 5 - Numerical Integration Practice 6 - Arrangements and matrices Part One: Arrangements Part II: Matrices Practice 7 - Systems of linear equations Practice 8 - Interpolation Practice 9 - Algorithm Design Techniques
标签： Practice Introduction Programming Practices
上传时间： 2013-12-16
上传用户：R50974
