特点 精确度0.1%满刻度 ±1位数 显示范围-19999-99999可任意规划 可直接量测直流电流/直流电压,无需另接辅助电源 尺寸小(24x48x50mm),稳定性高 分离式端子,配线容易 CE 认证 2.主要規格 辅助电源: None 精确度: 0.1% F.S. ±1 digit(1-100%F.S.) 输入抗阻 : >100Mohm(<2V range) >2Mohm(<2Vrange) < 0.25VA(current ranges) < 1000Vrms(>54V ranges) 最大过载能力: < 150Vrms(<54V ranges)
上传时间： 2013-10-08
上传用户：tiantwo
无刷电机 霍尔传感器 反电动势 控制 原理：无刷直流（Brushless Direct current， BLDC）电机是一种正快速普及的电机类型，它可在家用电器、汽车、航空航天、消费品、医疗、工业自动化设备和仪器等行业中使用。 正如名称指出的那样，BLDC 电机不用电刷来换向，而是使用电子换向。BLDC 电机和有刷直流电机以及感应电机相比，有许多优点。其中包括：
上传时间： 2013-11-24
上传用户：miaochun888
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上传时间： 2013-10-24
上传用户：s蓝莓汁
Abstract: This application note helps system designers choose the correct external components for use with the MAX16948 dualremote antenna LDO/switch, thus ensuring that automobile-regulated phantom antenna supply and output-current-monitoring circuitrymeet performance objectives. An electronic calculator is provided that helps specify the critical external components for theMAX16948, thus reducing design time. The calculator also determines the device's analog output voltage, output current-limitthreshold, and output current-sensing accuracies. The calculator includes new automatic Step By Step feature that assists designerswith component choice. To use the new automatic feature, click on the Step By Step button relative to the desired section.
上传时间： 2013-11-04
上传用户：lhll918
阐述了轨道交通列车定位技术。介绍了在轨道交通系统中列车定位技术的功能，国内外轨道交通中主要采用的列车定位方法，重点论述了几种主要定位技术，并从定位精度、闭塞制式、维护投资成本、抗干扰等方面进行分析比较。提出目前轨道交通定位技术应综合运用，取长补短，多种方法相互融合，才能满足轨道交通中对安全可靠性的要求。 Abstract: Rail train positioning technology is described. The paper introduces the funetions of the train positioning technology in the rail transit system， the main methods of train positioning do mestic and international rail， and focuses on several key methods， analyzes and compares from the positioning accuracy， block system, maintenance and investment cost， interference and so on， suggested that the current rail positioning technology should be integrated use of positioning method of meriging， learn from each other， to meet the reliability requirements of rail safety.
上传时间： 2013-11-25
上传用户：franktu
本软件是关于MAX338, MAX339的英文数据手册：MAX338, MAX339 8通道/双4通道、低泄漏、CMOS模拟多路复用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上传时间： 2013-11-12
上传用户：18711024007
This book is about the digital logic design of microprocessors. It is intended to provide both an understanding of the basic principles of digital logic design, and how these fundamental principles are applied in the building of complex microprocessor circuits using current technologies.
上传时间： 2013-10-14
上传用户：leyesome
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.
上传时间： 2013-11-23
上传用户：nanxia
PCB设计问题集锦 问：PCB图中各种字符往往容易叠加在一起，或者相距很近，当板子布得很密时，情况更加严重。当我用Verify Design进行检查时，会产生错误，但这种错误可以忽略。往往这种错误很多，有几百个，将其他更重要的错误淹没了，如何使Verify Design会略掉这种错误，或者在众多的错误中快速找到重要的错误。 答：可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：这是有关制造方面的一个检查，您没有相关设定，所以可以不检查。 问： 怎样导出jop文件？答：应该是JOB文件吧？低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件，方法如下STEP：FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件，再保存为JOB文件。 问： 怎样导入reu文件？答：在ECO与Design 工具盒中都可以进行，分别打开ECO与Design 工具盒，点击右边第2个图标就可以。 问： 为什么我在pad stacks中再设一个via:1(如附件）和默认的standardvi(如附件）在布线时V选择1，怎么布线时按add via不能添加进去这是怎么回事，因为有时要使用两种不同的过孔。答：PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件，如电源类只能用Standard VIA等等，这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问：为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答：首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问：我用ctrl+c复制线时怎设置原点进行复制，ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答： 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问：用(图4)进行修改线时拉起时怎总是往左边拉起(图5)，不知有什么办法可以轻易想拉起左就左，右就右。答： 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问： 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起，而你教程里都会好好的(图8)答：这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问： 尊敬的老师:您好！这个图已经画好了，但我只对（如图1）一种的完全间距进行检查，怎么错误就那么多，不知怎么改进。请老师指点。这个图在附件中请老师帮看一下，如果还有什么问题请指出来，本人在改进。谢！！！！！答：请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问： U101元件已建好，但元件框的拐角处不知是否正确，请帮忙CHECK 答：元件框等可以通过修改编辑来完成。问： U102和U103元件没建完全，在自动建元件参数中有几个不明白：如：SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值，还有这两个元件SILK怎么自动设置，以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答：Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间： 2014-01-03
上传用户：Divine
