pg059-axi-interconnect
标签： axi-interconnect 059 pgpg059-axi-interconnect
上传时间： 2016-05-04
上传用户：BLOSSOM93
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
axi协议的文档，介绍AMBA Advanced eXtensible Interface (AXI) Protocol
上传时间： 2013-04-24
上传用户：tongda
目的是利用嵌入在Xilinx FPGA中的MicroBlaze核实现基于AXI总线的双核嵌入式系统设计以及共享实现LED灯的时控.
标签： MicroBlaze SoPC AXI 总线
上传时间： 2014-12-30
上传用户：stewart·
AXI Reference Guide (AXI).pdf
上传时间： 2013-10-29
上传用户：libinxny
AXI Bus Functional Model v1.1 Product Brief.pdf
上传时间： 2015-01-01
上传用户：kbnswdifs
Rapid IO Interconnect Specification Physical Layer.
标签： Specification Interconnect Physical Rapid
上传时间： 2014-01-16
上传用户：极客
外围组件接口技术（Peripheral Component Interconnect PCI）是一种新型的高带宽、处理器无关的总线系统。它既可以作为中间层的总线也可以作为周边总线系统使用。与其他普通总线规范想对照，PCI 总线为高速I/O设备提供了更好的支持（比如图形适配器、网络接口控制器、磁盘控制器，等等）。现行的标准允许在33Mhz下使用64根数据线，纯传输速率可达2.11Gbps。但是PCI吸引人的地方不在于它的高速度，它适应了现代I/O设备对系统的要求，并且只需要很少的芯片就可以实现并支持其他总线系统。
标签： Interconnect Peripheral Component PCI
上传时间： 2017-01-17
上传用户：qb1993225
Local interconnect network LIN (bus interface)
标签： interconnect interface network Local
上传时间： 2017-08-06
上传用户：youlongjian0
