This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
ass="tags">标签： Verilog XAPP CPLD 143
ass="time">上传时间： 2013-11-11
ass="username">上传用户：y13567890
This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.
ass="tags">标签： XAPP CPLD VHDL 105
ass="time">上传时间： 2013-11-21
ass="username">上传用户：gtf1207
The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat of the FPGA package. as the interfaces get fasterand wider, choosing the right package has becomeone of the key considerations for the systemdesigner.
ass="tags">标签： Virtex 247 WP 高级封装
ass="time">上传时间： 2013-11-07
ass="username">上传用户：wanghui2438
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
ass="tags">标签： CoolRunner-II Xilinx XAPP CPLD
ass="time">上传时间： 2013-12-16
ass="username">上传用户：qwer0574
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
ass="tags">标签： PCI-X XAPP DIMM 708
ass="time">上传时间： 2013-11-24
ass="username">上传用户：18707733937
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGas are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
ass="tags">标签： XAPP FPGA Bank 520
ass="time">上传时间： 2013-11-06
ass="username">上传用户：wentianyou
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
ass="tags">标签： Modelling Guide Navy VHDL
ass="time">上传时间： 2013-11-20
ass="username">上传用户：pzw421125
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别as the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
ass="tags">标签： Verilog verilog System VHDL
ass="time">上传时间： 2014-03-03
ass="username">上传用户：zhtzht
Field Programmable Gate Arrays (FPGas) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
ass="time">上传时间： 2013-10-22
ass="username">上传用户：lmq0059
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
ass="tags">标签： allegro manual cx 教程
ass="time">上传时间： 2015-01-02
ass="username">上传用户：zhangyi99104144
