Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
ass="time">上传时间： 2013-10-12
ass="username">上传用户：kang1923
altera
ass="tags">标签： ALTERA FPGA Jtag 模式
ass="time">上传时间： 2014-01-02
ass="username">上传用户：pinksun9
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
ass="tags">标签： Base-Station Applications Single-Chip Transceiver
ass="time">上传时间： 2013-11-05
ass="username">上传用户：超凡大师
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. as today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
ass="tags">标签： AXI4 379 wp 即插即用
ass="time">上传时间： 2013-11-11
ass="username">上传用户：csgcd001
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
ass="tags">标签： Xilinx XAPP XSVF 503
ass="time">上传时间： 2015-01-02
ass="username">上传用户：时代将军
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
ass="tags">标签： Virtex XAPP 228 器件
ass="time">上传时间： 2014-01-24
ass="username">上传用户：15527161163
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. as a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. as a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
ass="tags">标签： Spartan XAPP FPGA 098
ass="time">上传时间： 2013-11-01
ass="username">上传用户：wojiaohs
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. as a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
ass="tags">标签： XAPP CPLD 444 配件
ass="time">上传时间： 2014-01-11
ass="username">上传用户：a471778
Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavior, because programmable parts encounter unknown variables – yourdesign and your power environment.
ass="tags">标签： Xilinx XAPP CPLD 440
ass="time">上传时间： 2013-11-24
ass="username">上传用户：253189838
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
ass="tags">标签： XAPP CPLD 144 电压
ass="time">上传时间： 2013-11-10
ass="username">上传用户：yy_cn
