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think in c++。chm版

ink in c++.chm C++编程思想经典书籍非常方便，需要的请下载吧。

标签： think chm in

上传时间： 2013-06-12

上传用户：yanming8525826
Protel99se鼠标增强软件2.0

Protel99se鼠标增强软件2.0: 2.0版本改名为“Protel99se鼠标增强软件”，是因为使用普通三键鼠标也可实现放大和缩小功能。 1.0版本功能：(软件名称：“Protel99se增加鼠标滚轮放大缩小功能”) 向上滚动滚轮 --> Zoom In 放大（PageUp键）向下滚动滚轮 --> Zoom Out 缩小（PageDown键）单击中键 --> Zoom Pan 移动屏幕 (Home键) 2.0版本新增功能： 1.在手动布局时，按鼠标左键移动元件时，再点击右键，可旋转元件。（非常好用的功能） 2.增加鼠标中键手形功能，按住中键，移动鼠标，放开中键，为一个手形功能。按中键向左移动 --> 在画线时退回上一步（退格键）按中键向右移动 --> 删除有焦点的对象（Delete键）按中键向上移动 --> 放置元件时，进入修改元件属性（Tab键）按中键向下移动 --> 放置元件时，用于旋转元件（空格键）按中键向左上移动 --> Zoom Out 缩小（PageDown键）按中键向右下移动 --> Zoom In 放大（PageUp键）按中键向右上移动 --> Clear 删除所有选择的对象（Ctrl+Delete键）按中键向左下移动 --> Fit All Objects 显示所有元件（Ctrl+PageDown键） 3.在PCB、SCH、PCBLib、SCHLib四个编辑器中都能实现本软件的所有功能。

标签： Protel 2.0 99 se

上传时间： 2013-07-02

上传用户：电子世界
基于FPGA的单总线(ONE-WIRE)协议的实现源代码.

基于FPGA的单总线(ONE-WIRE)协议的实现源代码.

标签： ONE-WIRE FPGA 单总线协议

上传时间： 2013-08-30

上传用户：wyc199288
电子书：Practical FPGA Programming in C

Practical FPGA Programming in C \r\nBy David Pellerin, Scott Thibault \r\nPublisher: Prentice Hall PTR \r\nPub Date: April 22, 2005 \r\nISBN: 0-13-154318-0 \r\nPages: 464 \r\n

标签： Programming Practical FPGA in

上传时间： 2013-08-31

上传用户：firstbyte
Building a RISC System in an FPGA

Building a RISC System in an FPGA

标签： Building System RISC FPGA

上传时间： 2013-09-04

上传用户：朗朗乾坤
Fpga Implementation Of Digital Timing Recovery In Software Radio Receiver

Fpga Implementation Of Digital Timing Recovery In Software Radio Receiver

标签： Implementation Recovery Receiver Software

上传时间： 2013-09-05

上传用户：panpanpan
FPGA in the software radio

FPGA in the software radio

标签： software radio FPGA the

上传时间： 2013-09-06

上传用户：lina2343
Many CAD users dismiss schematic capture as a necessary evil in the process of creating

Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, getting the des

标签： schematic necessary creating dismiss

上传时间： 2013-09-25

上传用户：baiom
Verilog Coding Style for Efficient Digital Design

In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

标签： Efficient Verilog Digital Coding

上传时间： 2013-11-22

上传用户：han_zh
Verilog编码中的非阻塞性赋值

One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

标签： Verilog 编码非阻塞性赋值

上传时间： 2013-10-17

上传用户：tb_6877751