In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上传时间： 2013-11-19
上传用户：shirleyYim
I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.
标签： microcontro Using 76X LPC
上传时间： 2013-12-30
上传用户：Artemis
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上传时间： 2013-10-21
上传用户：xiaozhiqban
红外遥控接收;=================================================;; zsMCU51实验板配套学习例程;; 中山单片机学习网 智佳科技;; 作者：逸风 QQ:105558851;; http://www.zsmcu.com; E-mail:info@zsmcu.com;=================================================ORG 0000HLJMP START;转入主程序ORG 0010HSTART:MAIN:JNB P2.2,IRLJMP MAIN;以下为进入P3.2脚外部中断子程序，也就是解码程序IR:MOV R6,#9SB:ACALL DELAY882 ;调用882微秒延时子程序JB P2.2,EXIT ;延时882微秒后判断P3.2脚是否出现高电平如果有就退出解码程序DJNZ R6, SB ;重复10次，目的是检测在8820微秒内如果出现高电平就退出解码程序;以上完成对遥控信号的9000微秒的初始低电平信号的识别。JNB P2.2, $ ;等待高电平避开9毫秒低电平引导脉冲ACALL DELAY2400JNB P2.2,IR_Rp ;ACALL DELAY2400 ;延时4.74毫秒避开4.5毫秒的结果码MOV R1,#1AH ;设定1AH为起始RAM区MOV R2,#4PP:MOV R3,#8JJJJ:JNB P2.2,$ ;等待地址码第一位的高电平信号LCALL DELAY882 ;高电平开始后用882微秒的时间尺去判断信号此时的高低电平状态MOV C,P2.2 ;将P3.2引脚此时的电平状态0或1存入C中 JNC UUU ;如果为0就跳转到UUULCALL DELAY1000UUU:MOV A,@R1 ;将R1中地址的给ARRC A ;将C中的值0或1移入A中的最低位MOV @R1,A ;将A中的数暂时存放在R1中DJNZ R3,JJJJ ;接收地址码的高8位INC R1 ;对R1中的值加1，换下一个RAMDJNZ R2,PP ;接收完16位地址码和8位数据码和8位数据，存放在1AH/1BH/1CH/1DH的RAM中MOV P1,1DH ;将按键的键值通过P1口的8个LED显示出来!CLR P2.3 ;蜂鸣器鸣响－嘀嘀嘀－的声音，表示解码成功LCALL DELAY2400LCALL DELAY2400LCALL DELAY2400SETB P2.3;蜂鸣器停止LJMP MAINIR_Rp:LJMP MAINEXIT:LJMP MAIN ;退出解码子程序;=============================882DELAY882: ;1.085x ((202x4)+5)=882MOV R7,#202DELAY882_A:NOPNOPDJNZ R7,DELAY882_ARET;=============================1000DELAY1000: ;1.085x ((229x4)+5)=999.285MOV R7,#229DELAY1000_A:NOPNOPDJNZ R7,DELAY1000_ARET;=============================2400
上传时间： 2013-11-01
上传用户：2525775
The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating systems.
上传时间： 2013-11-01
上传用户：ghostparker
MCS-51单片机实用子程序库 ;片内RAM初始化子程序IBCLR: MOV A,R0MOV R1,ACLR AIBC1 : MOV @R1,AINC R1DJNZ R7,IBC1RET;片外RAM初始化子程序EBCLR1: MOV A,ADDPLMOV DPL,AMOV A,ADDPHMOV DPH,ACLR CEBC11: MOVX @DPTR,AINC DPTRDJNZ R7,EBC11RET;片外RAM初始化子程序(双字节个单元)EBCLR2: MOV A,ADDPLMOV DPL,AMOV A,ADDPHMOV DPH,AMOV A,R7JZ EBC21INC R6EBC21: CLR AMOVX @DPTR,AINC DPTRDJNZ R7,EBC21DJNZ R6,EBC21RET;内部RAM数据复制程序;入口: R0,R7;占用资源: A;堆栈需求: 2字节
上传时间： 2013-10-10
上传用户：18602424091
电子发烧友网：针对目前电子发烧友网举办的“玩转FPGA：iPad2，赛灵思开发板等你拿”，小编在电话回访过程中留意到有很多参赛选手对Xilinx 公司的FPGA及其设计流程不是很熟悉，所以特意在此整理了一些相关知识，希望对大家有所帮助。当然也希望Xilinx FPGA爱好者能跟我们一起来探讨学习！ 本文主要帮助大家熟悉利用ISE进行Xilinx 公司FPGA 代码开发的基本流程。主要是帮助初学者了解和初步掌握 ISE 的使用，不需要 FPGA 的开发基础，所以对每个步骤并不进行深入的讨论。 图 实例显示成果图
上传时间： 2013-11-06
上传用户：时代将军
A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
上传时间： 2013-11-05
上传用户：Wwill
