The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8! Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects! This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever. Not just what to d why to do it! Use labview to build your own virtual workbench Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more Learn the "art" and best practices of effective labview development NEW: Streamline development with labview Express VIs NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
上传时间： 2013-10-14
上传用户：shawvi
Abstract: When people want portable music, they usually rely on battery-powered audio devices. With a bit of engineeringblood (or curiosity) running in your veins, it is not difficult to build a wireless Bluetooth® stereo audio system that can becontrolled with any device that has a Bluetooth connection and a music player
上传时间： 2013-10-09
上传用户：天空说我在
Abstract: After you park your car and go into your house, probably the last thing that you want to think about is someone stealing
上传时间： 2014-04-24
上传用户：athjac
Altium Designer 10是由Altium公司推出的一款开发软件，Altium Designer 10综合了电子产品一体化开发所需的所有必须技术和功能。Altium Designer 在单一设计环境中集成板级和FPGA系统设计、基于FPGA和分立处理器的嵌入式软件开发以及PCB版图设计、编辑和制造。并集成了现代设计数据管理功能,使得Altium Designer成为电子产品开发的完整解决方案－一个既满足当前，也满足未来开发需求的解决方案。 Altium Designer10 为您带来了一个全新的管理元 Altium Designer release 10器件的方法。其中包括新的用途系统、修改管理、新的生命周期和审批制度、实时供应链管理等更多的新功能! Altium Designer 10安装流程： 安装完后复制 AD10.Crack 文件夹下文件到安装目录。 1.运行AD10KeyGen，点击“打开模板”，加载license.ini，如想修改注册名，只需修改：TransactorName=Your Name，其中Your Name用你自己的名字替换，其它参数在单机版的情况下无需修改； 2.点击“生成协议”，保存生成的alf文件(文件名任意，如“jack ”)，并将其放到你的安装目录下； 3.将patch.exe放到你的安装目录下，运行patch，对安装目录下的dxp.exe文件补丁，注意运行破解时软件没有运行； 4.启动DXP，运行菜单DXP->My Account，点击Add Standalone License file，加载前面生成的license（.alf）文件后即能正常使用了。 资源是.bin格式的镜像文件，到网上下一个UltraISO打开后另存为iso或isz格式，用DAEMON Tools Lite虚拟光驱打开就能安装了。(或者安装一个快压打开) 安装提醒： 安装时有两个路径选择，第一个是安装主程序的；第二个是放置设计样例、元器件库文件、模板文件的，共3.3GB。如果你的C盘留的不够大，建议将3GB多的东西和主程序安装在一块儿。 安装完成后界面可能是英文的，如果想调出中文界面，则可以：DXP-->Preferences-->System-->General-->Localization--选中Use localized resources，保存设置后重新启动程序就有中文菜单了。 Altium Designer 10破解方法： 安装包里已经带有破解文件了，但没有AD10KeyGen这个文件，所以要把注册名改成自己的名字不方便。 1.运行AD10KeyGen，点击“打开模板”，加载license.ini，如想修改注册名，只需修改： TransactorName=Your Name 其中Your Name用你自己的名字替换，其它参数在单机版的情况下无需修改； 2.点击“生成协议”，保存生成的alf文件(文件名任意，如“jack ”)，并将其放到你的安装目录下； 3.将patch.exe放到你的安装目录下，运行patch，对安装目录下的dxp.exe文件补丁，注意运行破解时软件没有运行； 4.启动DXP，运行菜单DXP->My Account，点击Add Standalone License file，加载前面生成的license（.alf）文件后即能正常使用了。 注意： 1.局域网内用同一license不再提示冲突 2.仅供学习研究使用，勿用于非法用途。 相关资料：altium designer 10 破解教程
上传时间： 2013-11-10
上传用户：叶立炫95
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
标签： Considerations Guidelines and Design
上传时间： 2013-11-09
上传用户：ls530720646
使用Nios II软件构建工具 This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.
上传时间： 2013-10-12
上传用户：china97wan
Nios II 软件开发人员手册中的缓存和紧耦合存储器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上传时间： 2013-10-25
上传用户：虫虫虫虫虫虫
Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavior, because programmable parts encounter unknown variables – yourdesign and your power environment.
上传时间： 2013-11-24
上传用户：253189838
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2013-11-11
上传用户：zwei41
