Visual Assist X 10.6.1822.0（VC6.0智能插件）
上传时间： 2013-12-15
上传用户：ysystc670
MATLAB5[x]入门与提高.
标签： MATLAB5
上传时间： 2014-01-25
上传用户：fairy0212
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Allegro15[1].X培训教材
上传时间： 2014-01-08
上传用户：qzhcao
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上传时间： 2013-11-24
上传用户：18707733937
支持X/YModem和cis_b+协议的串口通讯程序
上传时间： 2014-01-17
上传用户：qweqweqwe
支持X/Y/Z Modem协议的传输文件的通讯程序
上传时间： 2015-01-03
上传用户：xg262122
X Windows下的迷宫程序
上传时间： 2015-01-04
上传用户：372825274
支持Windows 3.x、Windows 9x平台上的中文（GB、Big5）、日文（Shift JIS、EUC JIS)、韩文（KS C 5601）、HZ码的显示与输入,智能内码识别，支持屏幕取词翻译的16位程序(VC1.5编译)。作者：朱佳良
上传时间： 2013-12-28
上传用户：003030
支持SSL v2/v3, TLS, PKCS #5, PKCS #7, PKCS #11, PKCS #12, S/MIME, X.509v3证书等安全协议或标准的开发库编译用到NSPR
上传时间： 2014-01-27
上传用户：sammi
