演示linux下面top命令的源代码,top是用来查看系统CPU及资源占用比的.
上传时间： 2013-12-16
上传用户：ztj182002
这是从网上down的关于vc的自学书籍希望对大家能有帮助 独乐乐 不如大家乐
上传时间： 2013-12-21
上传用户：kelimu
Joey is j2me client server application for for mobile platform. Build on top j2mepolish
标签： application j2mepolish for platform
上传时间： 2016-09-29
上传用户：sz_hjbf
Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
标签： Compensation Conversion Designing MegaCore
上传时间： 2016-10-07
上传用户：wendy15
3D Statistical shape analysis by SHPARM method: code and paper. From the top group at UNC.
标签： Statistical analysis SHPARM method
上传时间： 2016-10-20
上传用户：wfl_yy
iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
标签： VHDL c_control vhd control
上传时间： 2016-10-30
上传用户：woshiayin
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
网上down的一个电机控制的，据说很吧u错啊，有兴趣可以看下啊。
上传时间： 2016-11-08
上传用户：13188549192
黑客防线下载系统(http://www.hacker.com.cn/down) 感谢使用本软件，有任何疑问请访问黑客防线官方网站（http://www.hacker.com.cn）并提出。我们将尽快为您解决。 更多精品黑客工具请访问：www.hacker.com.cn/vip
上传时间： 2014-06-09
上传用户：cx111111
