this code is a simulator to simulate the paging system such as first come first service. the comment in this code can help you to run it.
标签： first simulator the simulate
上传时间： 2014-01-03
上传用户：Late_Li
Verilog编写的M序列发生器，希望能对大家带来帮助。
上传时间： 2014-01-11
上传用户：zhliu007
A power control algorithm for 3G wcdma system, paper by Loutfi Nuaymi,
标签： algorithm control Loutfi Nuaymi
上传时间： 2013-12-23
上传用户：wmwai1314
Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法
标签： Verilog
上传时间： 2014-01-19
上传用户：ynzfm
Porting UCOS-II v2.0 to S3C2410 with File System v1.34 and RAM driver
标签： Porting UCOS-II S3C2410 System
上传时间： 2013-12-07
上传用户：ainimao
verilog 实现的jtag ip模块 包括了测试程序
上传时间： 2014-12-08
上传用户：叶山豪
Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
标签： instruction additional language example
上传时间： 2014-01-17
上传用户：yyyyyyyyyy
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
标签： system-on-chip integrated designed reusable
上传时间： 2013-12-20
上传用户：小眼睛LSL
PLD与8051接口的参考设计 Xilinx提供的verilog源代码
上传时间： 2014-01-01
上传用户：xzt
Fuzzy logic system VC classes
标签： classes system Fuzzy logic
上传时间： 2015-04-15
上传用户：diets
