这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。
上传时间： 2015-03-26
上传用户：qiao8960
The JDOM build system is based on Jakarta Ant, which is a Java building tool originally developed for the Jakarta Tomcat project but now used in many other Apache projects and extended by many developers.
标签： originally developed building Jakarta
上传时间： 2014-01-19
上传用户：xg262122
Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB开发
标签： system configuration recommends following
上传时间： 2015-03-27
上传用户：13188549192
This an adaptive receiver for a direct-sequence spread spectrum (DS-SS) system over an AWGN channel. The adaptive receiver block is modified from the LMS adaptive filter block in DSP Blockset. For DS-SS signal reception, the adaptive filter needs to have multi-rate operation. The input sample rate is equal to chip rate and the output is at symbol rate. Two rates are related by PG, processing gain
标签： direct-sequence adaptive receiver spectrum
上传时间： 2014-01-16
上传用户：D&L37
减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d
上传时间： 2015-03-28
上传用户：zycidjl
operating system concepts sixth edition windows XP updat 操作系统课后答案
标签： operating concepts edition windows
上传时间： 2015-03-28
上传用户：lps11188
這是一堆verilog的source code.包含許多常用的小電路.還不錯用.
上传时间： 2015-03-29
上传用户：lanwei
加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！
上传时间： 2013-12-10
上传用户：410805624
這是用verilog寫的一個簡單的處理器，雖然只具有5個指令，但是可以透過這個範例，來了解到cpu的架構，與如何開發處理器，相信會有很大的啟發。
标签： verilog
上传时间： 2014-12-08
上传用户：ikemada
手机文件浏览程序的另外一个版本！ SMan is a system utility that manages your UIQ device. It provides functionality which manufacturers did not provide or which are difficult or impossible to do manually. SMan helps keep your UIQ device running in a "healthy" state and, to a certain degree, allows you to customize the system behaviour of your device.
标签： functionality provides manages utility
上传时间： 2013-12-09
上传用户：独孤求源
