The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上传时间： 2013-10-28
上传用户：15501536189
《西门子系列PLC原理及应用》共有8章，第1章介绍了PLC的基本组成与工作原理；第2章介绍了西门子S7-200系列PLC的构成、性能及其工作方式；第3章详细地介绍了S7-200系列PLC专用编程软件STEP 7-Micro/WIN的主要功能与使用方法；第4～5章，结合实例介绍S7-200系列PLC的基本命令与功能命令；第6章讲述了S7-200系列PLC的网络通信知识与命令；第7章讲述了PLC控制系统的总体设计方法，并由浅入深地介绍了8个控制系统设计实例；第8章介绍了西门子S7-200系列PLC的安装与维护。
上传时间： 2013-12-31
上传用户：stampede
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-10-24
上传用户：teddysha
Cimatron E 7.0教程 使用Cimatron E 起草应用，建立部分或者组装图图表是可能的，由2D 风景组成。在画的每一个内有一条或更多床单，起草的符号和注释可能被增加并且编辑。 这些画图表包含象 起草标准那样的具体的特性，意见归因于，框架，模板等等。在各种各样的起草的概念将的这个练习过程中沿着边讨论Cimatron E的动态的能力。 1、打开一份起草的资料 Open up the Drafting application within Cimatron E. 2、现在起草应用的Cimatron 打开 资料在Cimatron E里使用起草被叫为一张画。 有一条床单的一张画被创造一份起草的资料自动创 造。 3、建立床单 一条床单包含一个一个模型，部分或者会议的2D 意见的布局。 除2D之外几何学建立使用 sketcher，起草符号，注释能被增加给床单。 无限的床单的数量能被归入一张画允许一象要求 的那样安排许多意见。
上传时间： 2014-12-31
上传用户：13817753084
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-11-23
上传用户：truth12
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
附件为：pdf转cad软件最新版 PDF Fly V7.1安装文件。还附有自制的Crack，把我的文件 贴到装好的目录下就行了!没有30天限制。 附pdf转cad软件使用教程： 1、pdf转cad软件的界面比较简单的，如下图，点击ADD添加你要转换的PDF文件，然后下一步 2、选择DXF格式，然后在右边的option里面还可以进行相关的设置 3、然后再下一步。step 3页面只要点最下面的 convert 就可以了 转完以后同样线条没有什么大问题的，只是文字肯定是被打碎的，你自己需要删除后重新输入要重新输入。
上传时间： 2013-10-22
上传用户：ardager
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-12
上传用户：kang1923
good good study ，day day up
上传时间： 2014-01-04
上传用户：waitingfy
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
标签： Solutions Analog Altera FPGAs
上传时间： 2013-10-27
上传用户：fredguo
