The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上传时间： 2013-10-24
上传用户：s蓝莓汁
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上传时间： 2013-11-07
上传用户：swing
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上传时间： 2014-12-30
上传用户：aysyzxzm
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上传时间： 2013-11-15
上传用户：努力努力再努力
ZigBee技术是一种应用于短距离范围内，低传输数据速率下的各种电子设备之间的无线通信技术。ZigBee名字来源于蜂群使用的赖以生存和发展的通信方式，蜜蜂通过跳ZigZag形状的舞蹈来通知发现的新食物源的位置、距离和方向等信息，以此作为新一代无线通讯技术的名称。ZigBee过去又称为“HomeRF Lite”、“RF-EasyLink”或“FireFly”无线电技术，目前统一称为ZigBee技术。 2、ZigBee技术的特点 自从马可尼发明无线电以来，无线通信技术一直向着不断提高数据速率和传输距离的方向发展。例如：广域网范围内的第三代移动通信网络（3G）目的在于提供多媒体无线服务，局域网范围内的标准从IEEE802.11的1Mbit/s到IEEE802.11g的54Mbit/s的数据速率。而当前得到广泛研究的ZigBee技术则致力于提供一种廉价的固定、便携或者移动设备使用的极低复杂度、成本和功耗的低速率无线通信技术。这种无线通信技术具有如下特点： 功耗低：工作模式情况下，ZigBee技术传输速率低，传输数据量很小，因此信号的收发时间很短，其次在非工作模式时，ZigBee节点处于休眠模式。设备搜索时延一般为30ms，休眠激活时延为15ms，活动设备信道接入时延为15ms。由于工作时间较短、收发信息功耗较低且采用了休眠模式，使得ZigBee节点非常省电，ZigBee节点的电池工作时间可以长达6个月到2年左右。同时，由于电池时间取决于很多因素，例如：电池种类、容量和应用场合，ZigBee技术在协议上对电池使用也作了优化。对于典型应用，碱性电池可以使用数年，对于某些工作时间和总时间（工作时间+休眠时间）之比小于1%的情况，电池的寿命甚至可以超过10年。 数据传输可靠：ZigBee的媒体接入控制层（MAC层）采用talk-when-ready的碰撞避免机制。在这种完全确认的数据传输机制下，当有数据传送需求时则立刻传送，发送的每个数据包都必须等待接收方的确认信息，并进行确认信息回复，若没有得到确认信息的回复就表示发生了碰撞，将再传一次，采用这种方法可以提高系统信息传输的可靠性。同时为需要固定带宽的通信业务预留了专用时隙，避免了发送数据时的竞争和冲突。同时ZigBee针对时延敏感的应用做了优化，通信时延和休眠状态激活的时延都非常短。 网络容量大：ZigBee低速率、低功耗和短距离传输的特点使它非常适宜支持简单器件。ZigBee定义了两种器件：全功能器件（FFD）和简化功能器件（RFD）。对全功能器件，要求它支持所有的49个基本参数。而对简化功能器件，在最小配置时只要求它支持38个基本参数。一个全功能器件可以与简化功能器件和其他全功能器件通话，可以按3种方式工作，分别为：个域网协调器、协调器或器件。而简化功能器件只能与全功能器件通话，仅用于非常简单的应用。一个ZigBee的网络最多包括有255个ZigBee网路节点，其中一个是主控（Master）设备，其余则是从属（Slave）设备。若是通过网络协调器（Network Coordinator），整个网络最多可以支持超过64000个ZigBee网路节点，再加上各个Network Coordinator可互相连接，整个ZigBee网络节点的数目将十分可观。 兼容性：ZigBee技术与现有的控制网络标准无缝集成。通过网络协调器（Coordinator）自动建立网络，采用载波侦听/冲突检测（CSMA-CA）方式进行信道接入。为了可靠传递，还提供全握手协议。
标签： zigbee
上传时间： 2013-11-24
上传用户：siguazgb
Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.
上传时间： 2014-03-25
上传用户：yyyyyyyyyy
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上传时间： 2013-10-11
上传用户：yuchunhai1990
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上传时间： 2013-10-28
上传用户：15501536189
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上传时间： 2014-01-17
上传用户：Altman
3 FPGA设计流程 完整的FPGA 设计流程包括逻辑电路设计输入、功能仿真、综合及时序分析、实现、加载配置、调试。FPGA 配置就是将特定的应用程序设计按FPGA设计流程转化为数据位流加载到FPGA 的内部存储器中，实现特定逻辑功能的过程。由于FPGA 电路的内部存储器都是基于RAM 工艺的，所以当FPGA电路电源掉电后，内部存储器中已加载的位流数据将随之丢失。所以，通常将设计完成的FPGA 位流数据存于外部存储器中，每次上电自动进行FPGA电路配置加载。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100电路为例，FPGA的配置模式有四种方案可选择：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通过芯片上的一组专/ 复用引脚信号完成的，主要配置功能信号如下： (1)M0、M1、M2：下载配置模式选择; (2)CLK：配置时钟信号; (3)DONE：显示配置状态、控制器件启动;
上传时间： 2013-11-18
上传用户：oojj
