A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2 sation cur rent int o t he p assive loop f ilte r during t he delay time of t he p hase f requency detect or ( PFD) , a maximum reduction of t he p hase noise by about 16dB can be achieved. Comp a red t o ot he r compensation met hods , t he tech2 nique p rop osed he re is relatively simple and easy t o implement . Key building blocks f or realizing t he noise cancel2 lation , including t he delay va riable PFD and comp ensation cur rent source , a re sp ecially designed. Bot h t he behavior level and circuit level SimulATion results a re p resented.
标签： sigma2delta compensate injecting artially
上传时间： 2013-12-18
上传用户：qlpqlq
OFDM通信系统的仿真。PDF文件，包括OFDM原理、程序讲解及运行结果。-OFDM communications system SimulATion. PDF documents, including OFDM principles, procedures and operations on the results.
上传时间： 2014-01-23
上传用户：66666
The NCTUns network simulator and emulator is developed at NCTU, Taiwan. Its predecessor is the Harvard network simulator (invented by Prof. S.Y. Wang in 1999). By using a novel SimulATion methodology, it can do several tasks that traditional network simulators cannot easily do.
标签： predecessor developed simulator emulator
上传时间： 2014-12-02
上传用户：txfyddz
this procedure is simulated document management system disk space management, Disk Management, directory management (single-level directory) of a SimulATion program, as well as university computer courses on operating system design a case, we only reference
标签： management Management procedure simulated
上传时间： 2017-02-05
上传用户：zhuoying119
Newton Game Dynamic 1.52 Delphi下基于GLScene的OpenGL游戏开发控件。功能非常强大和易于使用。 Advanced physics engine for real-time SimulATion of rigid bodies
标签： Advanced Dynamic GLScene physics
上传时间： 2014-01-18
上传用户：chongcongying
1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the design environments – SimulATion – Synthesis
标签： the Learn VHDL Understand
上传时间： 2017-02-18
上传用户：love_stanford
What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the SimulATion of designs ➥ Verilog is a discrete event time simulator What is VeriWell? ➥ VeriWell is a comprehensive implementation of Verilog HDL
标签： Verilog HDL 10149 Description
上传时间： 2017-02-18
上传用户：
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit SimulATion. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting
标签： synthesizable microcontro Synthetic PIC
上传时间： 2013-12-22
上传用户：妄想演绎师
Program uses a 2-D dynamic array to store any number of sets of randomly generated LOTO 6/49 numbers. SimulATion signed Lotto
标签： generated randomly Program dynamic
上传时间： 2017-02-19
上传用户：爱死爱死
3D FDTD 计算程序 ToyFDTD1 is a stripped-down, minimalist, 3-dimensional FDTD code that is published under the GNU General Public License. It is the first in the ToyFDTD series of codes, and it illustrates in heavily commented C and Fortran the basic tasks in implementing a simple 3D FDTD SimulATion.
标签： FDTD stripped-down dimensional minimalist
上传时间： 2013-12-25
上传用户：fhzm5658
