This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-06
上传用户：wentianyou
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上传时间： 2013-10-21
上传用户：huql11633
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上传时间： 2013-12-07
上传用户：bruce
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
标签： Methodology Design Reuse FPGA
上传时间： 2013-11-01
上传用户：shawvi
波长信号的解调是实现光纤光栅传感网络的关键，基于现有的光纤光栅传感器解调方法，提出一种基于FPGA的双匹配光纤光栅解调方法，此系统是一种高速率、高精度、低成本的解调系统，并且通过引入双匹配光栅有效地克服了双值问题同时扩大了检测范围。分析了光纤光栅的测温原理并给出了该方案软硬件设计，综合考虑系统的解调精度和FPGA的处理速度给出了基于拉格朗日的曲线拟合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
上传时间： 2013-10-10
上传用户：zxc23456789
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上传时间： 2013-11-19
上传用户：m62383408
【摘要】本文结合作者多年的印制板设计经验，着重印制板的电气性能，从印制板稳定性、可靠性方面，来讨论多层印制板设计的基本要求。【关键词】印制电路板；表面贴装器件；高密度互连；通孔【Key words】Printed Circuit Board；Surface Mounting Device；High Density Interface；Via一．概述印制板（PCB－Printed Circuit Board）也叫印制电路板、印刷电路板。多层印制板，就是指两层以上的印制板，它是由几层绝缘基板上的连接导线和装配焊接电子元件用的焊盘组成，既具有导通各层线路，又具有相互间绝缘的作用。随着SMT（表面安装技术）的不断发展，以及新一代SMD（表面安装器件）的不断推出，如QFP、QFN、CSP、BGA（特别是MBGA），使电子产品更加智能化、小型化，因而推动了PCB工业技术的重大改革和进步。自1991年IBM公司首先成功开发出高密度多层板（SLC）以来，各国各大集团也相继开发出各种各样的高密度互连（HDI）微孔板。这些加工技术的迅猛发展，促使了PCB的设计已逐渐向多层、高密度布线的方向发展。多层印制板以其设计灵活、稳定可靠的电气性能和优越的经济性能，现已广泛应用于电子产品的生产制造中。下面，作者以多年设计印制板的经验，着重印制板的电气性能，结合工艺要求，从印制板稳定性、可靠性方面，来谈谈多层制板设计的基本要领。
上传时间： 2013-10-08
上传用户：zhishenglu
讨论、研究高性能覆铜板对它所用的环氧树脂的性能要求，应是立足整个产业链的角度去观察、分析。特别应从HDI多层板发展对高性能CCL有哪些主要性能需求上着手研究。HDI多层板有哪些发展特点，它的发展趋势如何——这都是我们所要研究的高性能CCL发展趋势和重点的基本依据。而HDI多层板的技术发展，又是由它的应用市场——终端电子产品的发展所驱动（见图1）。 图1 在HDI多层板产业链中各类产品对下游产品的性能需求关系图 1．HDI多层板发展特点对高性能覆铜板技术进步的影响1.1 HDI多层板的问世，对传统PCB技术及其基板材料技术是一个严峻挑战20世纪90年代初，出现新一代高密度互连（High Density Interconnection，简称为 HDI）印制电路板——积层法多层板（Build—Up Multiplayer printed board，简称为 BUM）的最早开发成果。它的问世是全世界几十年的印制电路板技术发展历程中的重大事件。积层法多层板即HDI多层板，至今仍是发展HDI的PCB的最好、最普遍的产品形式。在HDI多层板之上，将最新PCB尖端技术体现得淋漓尽致。HDI多层板产品结构具有三大突出的特征：“微孔、细线、薄层化”。其中“微孔”是它的结构特点中核心与灵魂。因此，现又将这类HDI多层板称作为“微孔板”。HDI多层板已经历了十几年的发展历程，但它在技术上仍充满着朝气蓬勃的活力，在市场上仍有着前程广阔的空间。
上传时间： 2013-11-19
上传用户：zczc
Q01、如何使一条走线至两个不同位置零件的距离相同? 您可先在Design/Rule/High Speed/Matched Net Lengths的规则中来新增规则设定,最 后再用Tools/EqualizeNet Lengths 来等长化即可。 Q02、在SCHLIB中造一零件其PIN的属性，如何决定是Passive, Input, I/O, Hi- Z,Power,…..？在HELP中能找到说明吗？市面有关 SIM？PLD？的书吗？或贵公司有讲义？ 你可在零件库自制零件时点选零件Pin脚,并在Electrical Type里,可以自行设定PIN的 属性,您可参考台科大的Protel sch 99se 里 面有介绍关于SIM的内容。 Q03、请问各位业界前辈,如何能顺利读取pcad8.6版的线路图,烦请告知 Protel 99SE只能读取P-CAD 2000的ASCII档案格式,所以你必须先将P-CAD8.6版的格式 转为P-CAD 2000的档案格式,才能让Protel读取。
标签： Protel
上传时间： 2013-11-07
上传用户：tangsiyun
