Nios II内核详细实现
上传时间： 2015-01-01
上传用户：源码3
Quartus中生成MIF
上传时间： 2013-11-02
上传用户：lanhuaying
以Altera公司的Quartus Ⅱ 7.2作为开发工具，研究了基于FPGA的DDS IP核设计，并给出基于Signal Tap II嵌入式逻辑分析仪的仿真测试结果。将设计的DDS IP核封装成为SOPC Builder自定义的组件，结合32位嵌入式CPU软核Nios II，构成可编程片上系统（SOPC），利用极少的硬件资源实现了可重构信号源。该系统基本功能都在FPGA芯片内完成，利用 SOPC技术，在一片 FPGA 芯片上实现了整个信号源的硬件开发平台，达到既简化电路设计、又提高系统稳定性和可靠性的目的。
上传时间： 2013-12-22
上传用户：forzalife
Quartus软件的一般使用流程。
上传时间： 2013-11-12
上传用户：netwolf
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
标签： CoolRunner-II XAPP CPLD 380
上传时间： 2013-10-26
上传用户：kiklkook
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
标签： CoolRunner-II Xilinx XAPP CPLD
上传时间： 2013-12-16
上传用户：qwer0574
There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a wide variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).
标签： CoolRunner-II XAPP 904 LCD
上传时间： 2013-12-17
上传用户：haiya2000
SECS I, SECS II协议通讯源码
上传时间： 2015-01-04
上传用户：qq1604324866
轩辕剑外传II（源码）
标签： 源码
上传时间： 2014-01-06
上传用户：问题问题
UCOS-II移植到ATmega103用ICCAVR语言编写.rar
上传时间： 2013-12-27
上传用户：lizhen9880
