PW2205 develops a high efficiency synchronous step-down DC-DC converter capable of delivering5A OUTPUT current. PW2205 operates over a wide input voltage range from 4.5V to 30V andintegrates main switch and synchronous switch with very low RDS(ON) to minimize the conductionloss.PW2205 adopts the instant PWM architecture to achieve fast transient responses for high step downapplications and high efficiency at light loads. In addition, it operates at pseudo-constant frequencyof 500kHz under continuous conduction mode to minimize the size of inductor and capacitor
标签： pw2205
上传时间： 2022-02-11
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The PW2163 is a high efficiency 500 kHz synchronous step-down DC-DC converter capable ofdelivering 3A current. The PW2163 operates over a wide input voltage range from 4.5V to 18V andintegrates main switch and synchronous switch with very low RDS(ON) to minimize the conductionloss. Low OUTPUT voltage ripple and small external inductor and capacitor sizes are achieved with 500kHz switching frequency. It adopts the instant PWM architecture to achieve fast transient responsesfor high step down applications
标签： pw2163
上传时间： 2022-02-11
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The PW2162 is a fully integrated, high– efficiency 2A synchronous rectified step-down converter.The PW2162 operates at high efficiency over a wide OUTPUT current load range. This device offerstwo operation modes, PWM control and PFM Mode switching control, which allows a high efficiencyover the wider range of the load. The PW2162 requires a minimum number of readily availablestandard external components and is available in an 6-pin SOT23 ROHS compliant package.
标签： pw2162
上传时间： 2022-02-11
上传用户：d1997wayne
The PW2053 is a high-efficiency monolithic synchronous buck regulator using a constantfrequency, current mode architecture. The device is available in an adjustable version. Supply currentwith no load is 40uA and drops to <1uA in shutdown. The 2.5V to 5.5V input voltage range makesthe PW2053 ideally suited for single Li-Ion battery powered applications. 100% duty cycle provideslow dropout operation, extending battery life in portable systems. PWM/PFM mode operationprovides very low OUTPUT ripple voltage for noise sensitive applications. Switching frequency isinternally set at 1.2MHz, allowing the use of small surface mount inductors and capacitors. LowOUTPUT voltages are easily supported with the 0.6V feedback reference voltage
标签： pw2053
上传时间： 2022-02-14
上传用户：jason_vip1
PW1555 is a programmable current limit switch with input voltage range selection and OUTPUTvoltage clamping. Extremely low RDS(ON) of the integrated protection N-channel FET helps toreduce power loss during the normal operation. Programmable soft-start time controls the slew rateof the OUTPUT voltage during the start-up time. Independent enable control allows the complicatedsystem sequencing control. It integrates the over-temperature protection shutdown andautorecovery with hystersis
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上传时间： 2022-02-14
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高清电子书-C++ Primer Plus, 第6版英文版 1438页Learning C++ is an adventure of discovery, particularly because the language accommodates several programming paradigms, including object-oriented programming, generic programming, and the traditional procedural programming.The fifth edition of this book described the language as set forth in the ISO C++ standards, informally known as C++99 and C++03, or, sometimes as C++99/03. (The 2003 version was largely a technical correction to the 1999 standard and didn’t add any new features.) Since then, C++ continues to evolve.As this book is written, the international C++ Standards Committee has just approved a new version of the standard.This standard had the informal name of C++0x while in development, and now it will be known as C++11. Most contemporary compilers support C++99/03 quite well, and most of the examples in this book comply with that standard. But many features of the new standard already have appeared in some implementations, and this edition of C++ Primer Plus explores these new features. C++ Primer Plus discusses the basic C language and presents C++ features, making this book self-contained. It presents C++ fundamentals and illustrates them with short, to-the-point programs that are easy to copy and experiment with.You learn about input/OUTPUT (I/O), how to make programs perform repetitive tasks and make choices, the many ways to handle data, and how to use functions.You learn about the many features C++ has added to C, including the followi
标签： C++
上传时间： 2022-02-19
上传用户：trh505
5G通信系统中massive-MIMO-FBMC技术的结合概述摘要为了应对第五代移动通信（5G）中更高数据率和更低时延的需求，大规模MIMO （massive multiple-input multiple-OUTPUT）技术已经被提出并被广泛研究。大规模 MIMO技术能大幅度地提升多用户网络的容量。而在5G中的带宽研究方面，特别 是针对碎片频谱和频谱灵活性问题，现有的正交频分多址（Orthogonal Frequency Division Multiplexing, OFDM）技术不可能应对未来的挑战，新的波形方案需要 被设计出来。基于此，FBMC（filter bank multicarrier）技术由于具有比OFDM低 得多的带外频谱泄露而被受到重视，并已被标准推进组IMT-2020列为5G物理层 的主要备选方案之一。 本文首先回顾了5G中波形设计方案（主要是FBMC调制）和大规模多天线系 统（即massive MIMO）的现有工作和主要挑战。然后，简要介绍了基于Massive MIMO的FBMC系统中的自均衡性质，该性质可以用于减少系统所需的子载波数 目。同时，FBMC中的盲信道跟踪性质可以用于消除massive MIMO系统中的导频 污染问题。尽管如此，如何将FBMC技术应用于massive MIMO系统中的误码率、 计算复杂度、线性需求等方面仍然不明确，未来更多的研究工作需要在massive MIMO-FBMC方面展开来。 关键词：大规模MIMO；FBMC；自均衡；导频污染；盲均衡
上传时间： 2022-02-25
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Single chip TFT-LCD Controller/Driver with On-chip Frame Memory (FM) Display Resolution: 240*RGB (H) *320(V) Frame Memory Size: 240 x 320 x 18-bit = 1,382,400 bits LCD Driver OUTPUT Circuits- Source OUTPUTs: 240 RGB Channels- Gate OUTPUTs: 320 Channels- Common Electrode OUTPUT Display Colors (Color Mode)- Full Color: 262K, RGB=(666) max., Idle Mode Off- Color Reduce: 8-color, RGB=(111), Idle Mode On Programmable Pixel Color Format (Color Depth) for Various Display Data input Format- 12-bit/pixel: RGB=(444)- 16-bit/pixel: RGB=(565)- 18-bit/pixel: RGB=(666) MCU Interface- Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit)- 6/16/18 RGB Interface(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])- Serial Peripheral Interface(SPI Interface)- VSYNC Interface
上传时间： 2022-03-04
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ADC模数转换器件Altium Designer AD原理图库元件库SV text has been written to file : 4.4 - ADC模数转换器件.csvLibrary Component Count : 29Name Description----------------------------------------------------------------------------------------------------ADC0800 National 8-Bit Analog to Digital ConverterADC0809 ADC0831 ADCADC0832 ADC8 Generic 8-Bit A/D ConverterCLC532 High-Speed 2:1 Analog MultiplexerCS5511 National 16-Bit Analog to Digital ConverterDAC8 Generic 8-Bit D/A ConverterEL1501 Differential line Driver/ReceiverEL2082 Current-Mode MultiplierEL4083 Current Mode Four Quadrant MultiplierEL4089 DC Restored Video AmplifierEL4094 Video Gain Control/FaderEL4095 Video Gain Contol/Fader/MultiplexerICL7106 LMC6953_NSC PCI Local Bus Power SupervisorMAX4147 300MHz, Low-Power, High-OUTPUT-Current, Differential Line DriverMAX4158 350MHz 2-Channel Video Multiplexer-AmplifierMAX4159 350MHz 2-Channel Video Multiplexer-AmplifierMAX4258 250MHz, 2-Channel Video Multiplexer-AmplifierMAX4259 250MHz 2-Channel Video Multiplexer-AmplifierMAX951 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMAX952 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMC1496 Balanced Modulator/DemodulatorPLL100k Generic Phase Locked LoopPLL10k Generic Phase Locked LoopPLL5k Generic Phase Locked LoopPLLx Generic Phase Locked Loop水位计
标签： adc 模数转换 altium designer
上传时间： 2022-03-13
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电子书-RTL Design Style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is OUTPUT when the reset signal is asynchronously input, and ’1’ is OUTPUT when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is OUTPUT following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
标签： RTL verilog hdl
上传时间： 2022-03-21
上传用户：canderile
