随着系统设计复杂性和集成度的大规模提高，电子系统设计师们正在从事100MHZ以上的电路设计，总线的工作频率也已经达到或者超过50MHZ，有一大部分甚至超过100MHZ。目前约80% 的设计的时钟频率超过50MHz，将近50% 以上的设计主频超过120MHz，有20%甚至超过500M。当系统工作在50MHz时，将产生传输线效应和信号的完整性问题；而当系统时钟达到120MHz时，除非使用高速电路设计知识，否则基于传统方法设计的PCB将无法工作。因此，高速电路信号质量仿真已经成为电子系统设计师必须采取的设计手段。只有通过高速电路仿真和先进的物理设计软件，才能实现设计过程的可控性。传输线效应基于上述定义的传输线模型，归纳起来，传输线会对整个电路设计带来以下效应。 · 反射信号Reflected signals · 延时和时序错误Delay & Timing errORs · 过冲(上冲/下冲)Overshoot/Undershoot · 串扰Induced Noise (OR crosstalk) · 电磁辐射EMI radiation
上传时间： 2013-11-16
上传用户：lx9076
Silicon Motion, Inc. has made best effORts to ensure that the infORmation contained in this document is accurate andreliable. However, the infORmation is subject to change without notice. No responsibility is assumed by SiliconMotion, Inc. fOR the use of this infORmation, nOR fOR infringements of patents OR other rights of third parties.Copyright NoticeCopyright 2002, Silicon Motion, Inc. All rights reserved. No part of this publication may be reproduced, photocopied,OR transmitted in any fORm, without the priOR written consent of Silicon Motion, Inc. Silicon Motion, Inc. reserves theright to make changes to the product specification without reservation and without notice to our users
标签： GUIDELINES LAYOUT 320 PCB
上传时间： 2014-12-24
上传用户：zhaistone
Integrated EMI/Thermal Design fORSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements fOR the degree of Integrated EMI/Thermal Design fORSwitching Power SuppliesWei Zhang(ABSTRACT)This wORk presents the modeling and analysis of EMI and thermal perfORmancefOR switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfOR EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically OR by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted fOR the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built fOR the components. Thermal perfORmance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductOR design examples are checkedfrom both the EMI and thermal point of view. Insightful infORmation is obtained.
上传时间： 2013-11-10
上传用户：1595690
This document provides practical, common guidelines fOR incORpORating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer OR mORe server baseboard designs. Guidelines and constraints in this document are intended fOR use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connectOR. This document is intended to cover all majOR components of the physical interconnect including design guidelines fOR the PCB traces, vias and AC coupling capacitORs, as well as add-in card edge-finger and connectOR considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate perfORmance of the interconnect fOR all layouts and implementations. TherefORe, designers should consider modeling and simulation of the interconnect in ORder to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight impORtant constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
Boost LED drivers are often used to drive LEDs in series. If an LED fails while open,overvoltage protection (OVP) is necessary to avoid the damage to a boost integrated circuit (IC) OR output capacitOR. This application repORt presents the solutions to increase the TPS61043 LED driver OVP threshold.
标签： Overvoltage Protection Solutions Driver
上传时间： 2013-10-14
上传用户：jiangfire
模块电源的电气性能是通过一系列测试来呈现的，下列为一般的功能性测试项目，详细说明如下： 电源调整率(Line Regulation) 负载调整率(Load Regulation) 综合调整率(Conmine Regulation) 输出涟波及杂讯(Ripple & Noise) 输入功率及效率(Input Power, Efficiency) 动态负载或暂态负载(Dynamic OR Transient Response) 起动(Set-Up)及保持(Hold-Up)时间 常规功能(Functions)测试 1. 电源调整率 电源调整率的定义为电源供应器于输入电压变化时提供其稳定输出电压的能力。测试步骤如下：于待测电源供应器以正常输入电压及负载状况下热机稳定后，分别于低输入电压(Min)，正常输入电压(NORmal)，及高输入电压(Max)下测量并记录其输出电压值。 电源调整率通常以一正常之固定负载(Nominal Load)下，由输入电压变化所造成其输出电压偏差率(deviation)的百分比，如下列公式所示： [Vo(max)-Vo(min)] / Vo(nORmal) 2. 负载调整率 负载调整率的定义为开关电源于输出负载电流变化时，提供其稳定输出电压的能力。测试步骤如下：于待测电源供应器以正常输入电压及负载状况下热机稳定后，测量正常负载下之输出电压值，再分别于轻载(Min)、重载(Max)负载下，测量并记录其输出电压值(分别为Vo(max)与Vo(min))，负载调整率通常以正常之固定输入电压下，由负载电流变化所造成其输出电压偏差率的百分比，如下列公式所示： [Vo(max)-Vo(min)] / Vo(nORmal) 3. 综合调整率 综合调整率的定义为电源供应器于输入电压与输出负载电流变化时，提供其稳定输出电压的能力。这是电源调整率与负载调整率的综合，此项测试系为上述电源调整率与负载调整率的综合，可提供对电源供应器于改变输入电压与负载状况下更正确的性能验证。 综合调整率用下列方式表示：于输入电压与输出负载电流变化下，其输出电压之偏差量须于规定之上下限电压范围内(即输出电压之上下限绝对值以内)或某一百分比界限内。 4. 输出杂讯 输出杂讯(PARD)系指于输入电压与输出负载电流均不变的情况下，其平均直流输出电压上的周期性与随机性偏差量的电压值。输出杂讯是表示在经过稳压及滤波后的直流输出电压上所有不需要的交流和噪声部份(包含低频之50/60Hz电源倍频信号、高于20 KHz之高频切换信号及其谐波，再与其它之随机性信号所组成))，通常以mVp-p峰对峰值电压为单位来表示。 一般的开关电源的规格均以输出直流输出电压的1%以内为输出杂讯之规格，其频宽为20Hz到20MHz。电源实际工作时最恶劣的状况(如输出负载电流最大、输入电源电压最低等)，若电源供应器在恶劣环境状况下，其输出直流电压加上杂讯后之输出瞬时电压，仍能够维持稳定的输出电压不超过输出高低电压界限情形，否则将可能会导致电源电压超过或低于逻辑电路(如TTL电路)之承受电源电压而误动作，进一步造成死机现象。 同时测量电路必须有良好的隔离处理及阻抗匹配，为避免导线上产生不必要的干扰、振铃和驻波，一般都采用双同轴电缆并以50Ω于其端点上，并使用差动式量测方法(可避免地回路之杂讯电流)，来获得正确的测量结果。 5. 输入功率与效率 电源供应器的输入功率之定义为以下之公式： True Power = Pav(watt) = Vrms x Arms x Power FactOR 即为对一周期内其输入电压与电流乘积之积分值，需注意的是Watt≠VrmsArms而是Watt=VrmsArmsxP.F.，其中P.F.为功率因素(Power FactOR)，通常无功率因素校正电路电源供应器的功率因素在0.6～0.7左右，其功率因素为1～0之间。 电源供应器的效率之定义为为输出直流功率之总和与输入功率之比值。效率提供对电源供应器正确工作的验证，若效率超过规定范围，即表示设计或零件材料上有问题，效率太低时会导致散热增加而影响其使用寿命。 6. 动态负载或暂态负载 一个定电压输出的电源，于设计中具备反馈控制回路，能够将其输出电压连续不断地维持稳定的输出电压。由于实际上反馈控制回路有一定的频宽，因此限制了电源供应器对负载电流变化时的反应。若控制回路输入与输出之相移于增益(Unity Gain)为1时，超过180度，则电源供应器之输出便会呈现不稳定、失控或振荡之现象。实际上，电源供应器工作时的负载电流也是动态变化的，而不是始终维持不变(例如硬盘、软驱、CPU或RAM动作等)，因此动态负载测试对电源供应器而言是极为重要的。可编程序电子负载可用来模拟电源供应器实际工作时最恶劣的负载情况，如负载电流迅速上升、下降之斜率、周期等，若电源供应器在恶劣负载状况下，仍能够维持稳定的输出电压不产生过高激(Overshoot)或过低(Undershoot)情形，否则会导致电源之输出电压超过负载组件(如TTL电路其输出瞬时电压应介于4.75V至5.25V之间，才不致引起TTL逻辑电路之误动作)之承受电源电压而误动作，进一步造成死机现象。 7. 启动时间与保持时间 启动时间为电源供应器从输入接上电源起到其输出电压上升到稳压范围内为止的时间，以一输出为5V的电源供应器为例，启动时间为从电源开机起到输出电压达到4.75V为止的时间。 保持时间为电源供应器从输入切断电源起到其输出电压下降到稳压范围外为止的时间，以一输出为5V的电源供应器为例，保持时间为从关机起到输出电压低于4.75V为止的时间，一般值为17ms或20ms以上，以避免电力公司供电中于少了半周或一周之状况下而受影响。 8. 其它 在电源具备一些特定保护功能的前提下，还需要进行保护功能测试，如过电压保护(OVP)测试、短路保护测试、过功保护等
上传时间： 2013-10-22
上传用户：zouxinwang
A light-emitting diode (LED) is a semiconductOR device that emits narrow-spectrum incoherent light when fORward-biased.The colOR of the emitted light depends on the chemical composition of the semiconductOR material used, and can benear-ultraviolet, visible OR infrared. LEDs are mORe prevalent today than ever befORe, replacing traditional incandescent andfluORescent bulbs in many lighting applications. Incandescents use a heated filament, are subject to breakage and burnoutand operate at a luminous efficiency of 2% to 4%. FluORescents are mORe efficient, at 7% to 12%, but require highdrive voltage and contain mercury, a toxic substance that may be eventually banned in certain countries. LEDs, however,produce light directly through electroluminescence, operate at low voltage and can deliver over 20% luminous efficiency.
上传时间： 2013-11-07
上传用户：xiaoyuer
Abstract: We don't expect manufacturers to produce clothes that in one size that fits everyone. In thesame way, one ESD component can't solve all issues—each application has different ESD requirements.Knowing that "one size fits all" cannot apply to power design, the power designer, OR the engineering"super hero," must consider all the potential disruptions to a steady flow of power and thenvarious waysto mitigate them. This tutORial describes voltage- and current-limiting devices and risetime reducers tomanage the power. It also points to free and low-cost software tools to help design lowpass filters, checkcapacitOR self-resonance, and simulate circuits.
上传时间： 2013-11-18
上传用户：zhouxuepeng1
Abstract: Stuxnet, a sophisticated virus that damaged Iran's nuclear capability, should be an eye openerfOR the wORld. We can choose to learn something very narrow (how to combat the Stuxnet virus) OR wecan choose to focus on the larger goal of thwarting the next type of creative cyber attack. UnfORtunately,critical industrial infrastructure is not currently designed with security as a key goal, leaving open multipleavenues fOR an educated and funded attacker to create massive problems. This tutORial outlines somebasic concepts that engineers and product definers should consider to make sure their new projects stayahead of future threats.
上传时间： 2013-11-17
上传用户：llwap
Abstract: Some power architectures require the power supply sequencer (OR system manager) to controldownstream power MOSFETs to allow power to flow into branch circuits. This application note explains howsystem power sequencing and level shifting can be accomplished using a low-voltage system manager
上传时间： 2013-11-02
上传用户：wys0120
