Cortex-M3 技术参考手册 Cortex-M3是一个32位的核，在传统的单片机领域中，有一些不同于通用32位CPU应用的要求。谭军举例说，在工控领域，用户要求具有更快的中断速度，Cortex-M3采用了Tail-Chaining中断技术，完全基于硬件进行中断处理，最多可减少12个时钟周期数，在实际应用中可减少70%中断。 单片机的另外一个特点是调试工具非常便宜，不象ARM的仿真器动辄几千上万。针对这个特点，Cortex-M3采用了新型的单线调试(Single Wire)技术，专门拿出一个引脚来做调试，从而节约了大笔的调试工具费用。同时，Cortex-M3中还集成了大部分存储器控制器，这样工程师可以直接在MCU外连接Flash，降低了设计难度和应用障碍。 ARM Cortex-M3处理器结合了多种突破性技术，令芯片供应商提供超低费用的芯片，仅33000门的内核性能可达1.2DMIPS/MHz。该处理器还集成了许多紧耦合系统外设，令系统能满足下一代产品的控制需求。ARM公司希望Cortex-M3核的推出，能帮助单片机厂商实. Cortex的优势应该在于低功耗、低成本、高性能3者(或2者)的结合。 Cortex如果能做到 合理的低功耗(肯定要比Arm7 & Arm9要低，但不大可能比430、PIC、AVR低) ＋ 合理的高性能(10~50MIPS是比较可能出现的范围) ＋ 适当的低成本(1~5$应该不会奇怪)。 简单的低成本不大可能比典型的8位MCU低。对于已经有8位MCU的厂商来说，比如Philips、Atmel、Freescale、Microchip还有ST和Silocon Lab，不大可能用Cortex来打自己的8位MCU。对于没有8位MCU的厂商来说，当然是另外一回事，但他们在国内进行推广的实力在短期内还不够。 对于已经有32位ARM的厂商来说，比如Philips、Atmel、ST，又不大可能用Cortex来打自己的Arm7/9，对他们来说，比较合理的定位把Cortex与Arm7/9错开，即<40MIPS的性能＋低于Arm7的价格，当然功耗也会更低些；当然这样做的结果很可能是，断了16位MCU的后路。 对于仍然在推广16位MCU的厂商来说，比如Freescal、Microchip，处境比较尴尬，因为Cortex基本上可以完全替代16位MCU。 所以，未来的1～2年，来自新厂商的Cortex比较值得期待－包括国内的供应商；对于已有32位ARM的厂商，情况比较有趣；对于16位MCU的厂商，反应比较有意思。 关于编程模式 Cortex－M3处理器采用ARMv7-M架构，它包括所有的16位Thumb指令集和基本的32位Thumb-2指令集架构，Cortex-M3处理器不能执行ARM指令集。 Thumb-2在Thumb指令集架构（ISA）上进行了大量的改进，它与Thumb相比，具有更高的代码密度并提供16/32位指令的更高性能。 关于工作模式 Cortex-M3处理器支持2种工作模式：线程模式和处理模式。在复位时处理器进入“线程模式”，异常返回时也会进入该模式，特权和用户（非特权）模式代码能够在“线程模式”下运行。 出现异常模式时处理器进入“处理模式”，在处理模式下，所有代码都是特权访问的。 关于工作状态 Coretx-M3处理器有2种工作状态。 Thumb状态：这是16位和32位“半字对齐”的Thumb和Thumb-2指令的执行状态。 调试状态：处理器停止并进行调试，进入该状态。
上传时间： 2013-12-04
上传用户：坏坏的华仔
PCF2119x是一款低功耗的CMOS型LCD控制器和驱动器，可以驱动一块点阵LCD显示2行每行16个5×8格式的字符，或者显示1行每行32个5×8格式的字符。PCF2119x单片（无需其他外围器件）提供显示所需的所有必要功能，包括片内产生LCD偏置电压。PCF2119x的这些特性使得其需要的外围器件极少并且能降低系统的电流损耗。PCF2119x可通过4或8位总线或者2-wire的I2C总线与大多数微控制器连接。该芯片包含一个字符发生器并且可以显示英文、数字和假名（日语）字符。
上传时间： 2013-11-06
上传用户：dalidala
CAT5110/18/19/23/24/25 linear-taper digitally programmable potentiometers perform the same function as a mechanical potentiometer or a variable resistor. These devices consist of a fixed resistor and a wiper contact with 32-tap points that are digitally controlled through a2-wire up/down serial interface.
上传时间： 2013-11-22
上传用户：541657925
This application report discusses the design of non-invasive optical plethysmographyalso called as pulsoximeter using the MSP430FG437 Microcontroller (MCU). Thepulsoximeter consists of a peripheral probe combined with the MCU displaying theoxygen saturation and pulse rate on a LCD glass. The same sensor is used for bothheart-rate detection and pulsoximetering in this application. The probe is placed on aperipheral point of the body such as a finger tip, ear lobe or the nose. The probeincludes two light emitting diodes (LEDs), one in the visible red spectrum (660nm) andthe other in the infrared spectrum (940nm). The percentage of oxygen in the body isworked by measuring the intensity from each frequency of light after it transmitsthrough the body and then calculating the ratio between these two intensities.
标签： Pulsoximeter Single-Chip Des
上传时间： 2013-10-27
上传用户：黑漆漆
The HCS12X family is the successor to the HCS12family, with many additional features. One new feature isthe increased memory available to the CPU and themethods available to access it. This document focuses onthe improved memory map configuration.
上传时间： 2013-11-13
上传用户：王者A
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上传时间： 2013-11-21
上传用户：q123321
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register.
上传时间： 2014-12-28
上传用户：nshark
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
标签： 4channel transla level 9519
上传时间： 2013-11-19
上传用户：jisiwole
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上传时间： 2013-10-09
上传用户：3294322651
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
标签： 4channel multiple 9544A 9544
上传时间： 2014-12-28
上传用户：潜水的三贡
