The PCA9672 provides general purpose remote I/O expansion for most microcontrollerfamilies via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plusfamily.The PCA9672 is a drop-in upgrade for the PCF8574 providing higher Fast-mode Plus(Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(200 mA versus 100 mA) that supports having all LEDs on at the same time and moredevice addresses (16 versus 8) are available to allow many more devices on the buswithout address conflicts.
上传时间： 2013-10-23
上传用户：jasonheung
The PCA9673 provides general purpose remote I/O expansion for most microcontrollerfamilies via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plusfamily.The PCA9673 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus(Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time andmore device addresses (16 versus 8) are available to allow many more devices on the buswithout address conflicts.
上传时间： 2013-10-29
上传用户：wkchong
The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-modePlus I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(200 mA versus 100 mA) that supports having all LEDs on at the same time and moredevice addresses (64 versus 8) are available to allow many more devices on the buswithout address conflicts.
上传时间： 2013-10-22
上传用户：wwwwwen5
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-07
上传用户：songrui
NNS-701 是專為移動裝置設計的全功能NFC (Near Field Communication)控制器芯片。
上传时间： 2013-10-11
上传用户：蠢蠢66
为满足无线网络技术具有低功耗、节点体积小、网络容量大、网络传输可靠等技术要求，设计了一种以MSP430单片机和CC2420射频收发器组成的无线传感节点。通过分析其节点组成，提出了ZigBee技术中的几种网络拓扑形式，并研究了ZigBee路由算法。针对不同的传输要求形式选用不同的网络拓扑形式可以尽大可能地减少系统成本。同时针对不同网络选用正确的ZigBee路由算法有效地减少了网络能量消耗，提高了系统的可靠性。应用试验表明，采用ZigBee方式通信可以提高传输速率且覆盖范围大，与传统的有线通信方式相比可以节约40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
上传时间： 2013-10-09
上传用户：robter
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-05
上传用户：超凡大师
这是一篇关于turbo码的原始论文，Near optimum error correcting cod ing and decoding turbo codes，可供学习参考之用。
上传时间： 2014-01-24
上传用户：pkkkkp
