8051工作于11.0592MHZ,RAM扩展为128KB的628128,FlashRom扩展为128KB的AT29C010A\r\n 128KB的RAM分成4个区(Bank) 地址分配为0x0000-0x7FFF\r\n 128KB的FlashRom分成8个区(Bank) 地址分配为0x8000-0xBFFF\r\n 为了使8051能访问整个128KB的RAM空间和128KB的FlashRom空间,在CPLD内建两个寄存器\r\n RamBankReg和FlashRomBankReg用于存放高位地址
上传时间： 2013-08-30
上传用户：cainaifa
自己现在用的CPLD下载线，用74HC244芯片\r\n要注意设置下载模式
上传时间： 2013-08-31
上传用户：dancnc
\r\n经典的Protel99se入门教程，孙辉著北京邮电大学出版社出版
上传时间： 2013-09-11
上传用户：Yukiseop
用于定量表示ADC动态性能的常用指标有六个，分别是：SINAD(信纳比)、ENOB(有效位 数)、SNR(信噪比)、THD(总谐波失真)、THD + N(总谐波失真加噪声)和SFDR(无杂散动态 范围)
上传时间： 2014-01-22
上传用户：鱼哥哥你好
基于N沟道MOS管H桥驱动电路设计与制作
上传时间： 2014-08-01
上传用户：1109003457
计数器是一种重要的时序逻辑电路，广泛应用于各类数字系统中。介绍以集成计数器74LS161和74LS160为基础，用归零法设计N进制计数器的原理与步骤。用此方法设计了3种36进制计数器，并用Multisim10软件进行仿真。计算机仿真结果表明设计的计数器实现了36进制计数的功能。基于集成计数器的N进制计数器设计方法简单、可行，运用Multisim 10进行电子电路设计和仿真具有省时、低成本、高效率的优越性。
上传时间： 2013-10-11
上传用户：gtzj
在理论模型的基础上探讨了电子势垒的形状以及势垒形状随外加电压的变化, 并进行定量计算, 得出隧穿电压随杂质掺杂浓度的变化规律。所得结论与硅、锗p-n 结实验数据相吻合, 证明了所建立的理论模型在定量 研究p-n 结的隧道击穿中的合理性与实用性。该理论模型对研究一般材料或器件的隧道击穿具有重要的借鉴意义。
上传时间： 2013-10-31
上传用户：summery
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
标签： Converters Defini DAC
上传时间： 2013-10-30
上传用户：stvnash
N+缓冲层设计对PT-IGBT器件特性的影响至关重要。文中利用Silvaco软件对PT-IGBT的I-V特性进行仿真。提取相同电流密度下，不同N+缓冲层掺杂浓度PT-IGBT的通态压降，得到了通态压降随N+缓冲层掺杂浓度变化的曲线，该仿真结果与理论分析一致。对于PT-IGBT结构，N+缓冲层浓度及厚度存在最优值，只要合理的选取可以有效地降低通态压降。
上传时间： 2013-11-12
上传用户：thesk123
高的工作电压高达100V N双N沟道MOSFET同步驱动 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
上传时间： 2013-10-24
上传用户：wd450412225
