介绍一种基于单片机的多路温度采集及监控系统，能够测量6路温度信号，具有计算机联网功能，各测量点可以单独监控和设置，可根据用户的需求自动控制。测量温度范围为-10 ℃～200 ℃，控制方式采用模拟量调压模式。该系统具有控制精度高、冲击小等特点。 Abstract: A temperature collecting and surveillance-controlling system based on sing-chip microcomputer is introduced. It can measure 6 channel signal of the temperature,and it has a function of network connection.The temperature measure points can be monitored and located, it can be controlled automatic according to user’s demand.The temperature range is -10℃ to 200℃.The MODEL of control is adjustable voltage with simulation. It features high precision and little impact.
上传时间： 2013-10-23
上传用户：bjgaofei
LLCR Pin Socket Testing with the MODEL 3732 High Density Matrix Card Computer processors (CPUs) today have come a long way from the computer processors of the past. They draw more power, run at lower voltages, and have more pins than ever before.
上传时间： 2013-10-24
上传用户：whenfly
MPLAB C30用户指南(英文) HIGHLIGHTSThe information covered in this chapter is as follows:• About this Guide• Recommended Reading• Troubleshooting• The Microchip Web Site• Development Systems Customer Notification Service• Customer Support Document LayoutThe document layout is as follows:• Chapter 1: Compiler Overview – describes MPLAB C30, development tools andfeature set.• Chapter 2: Differences between MPLAB C30 and ANSI C – describes thedifferences between the C language supported by MPLAB C30 syntax and thestandard ANSI-89 C.• Chapter 3: Using MPLAB C30 – describes how to use the MPLAB C30 compilerfrom the command line.• Chapter 4: MPLAB C30 Runtime Environment – describes the MPLAB C30runtime MODEL, including information on sections, initialization, memory MODELs, thesoftware stack and much more.• Chapter 5: Data Types – describes MPLAB C30 integer, floating point and pointerdata types.• Chapter 6: Device Support Files – describes the MPLAB C30 header and registerdefinition files, as well as how to use with SFR’s.• Chapter 7: Interrupts – describes how to use interrupts.• Chapter 8: Mixing Assembly Language and C Modules – provides guidelines tousing MPLAB C30 with MPLAB ASM30 assembly language modules.
上传时间： 2013-10-21
上传用户：13925096126
C51使用手册 .pdf 第二节内存区域(Memory Areas)1. Pragram Area由Code 说明可有多达64kBytes 的程序存储器2. Internal Data Memory:内部数据存储器可用以下关键字说明data 直接寻址区为内部RAM 的低128 字节00H 7FHidata 间接寻址区 包括整个内部RAM 区00H FFHbdata 可位寻址区 20H 2FH3. External Data Memory外部RAM 视使用情况可由以下关键字标识xdata 可指定多达64KB 的外部直接寻址区地址范围0000H 0FFFFHpdata 能访问1 页(25bBytes)的外部RAM 主要用于紧凑模式(Compact MODEL)4. Speciac Function Register Memory
上传时间： 2013-11-19
上传用户：busterman
怎样写testbench-xilinx 在ISE 环境中， 当前资源操作窗显示了资源管理窗口中选中的资源文件能进行的相关操作。在资源管理窗口选中了 testbench 文件后，在当前资源操作窗显示的 MODELSim Simulator 中显示了4种能进行的模拟操作，分别是：Simulator Behavioral MODEL（功能仿真）、Simulator Post-translate VHDL MODEL（翻译后仿真）、Simulator Post-Map VHDL MODEL（映射后仿真）、Simulator Post-Place & Route VHDL MODEL（布局布线后仿真） 。如
标签： testbench-xilinx
上传时间： 2013-11-14
上传用户：467368609
This application note describes how to decode standard DTMF tones using the minimum number of external discrete components and a PIC. The two examples use a PIC which has an 8 bit timer and either a comparator or an ADC, although it can be modified for use on a PIC which has only digital I/O. The Appendices have example code for the 16C662 (with comparator) and 16F877 (using the ADC). As the majority of the Digital Signal Processing is done in software, little is required in the way of external signal conditioning. Software techniques are used to MODEL the individual elements of a DTMF Decoder IC.
上传时间： 2013-11-21
上传用户：zhaoke2005
winCE msdn讲座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment MODEL OverviewWindows XP Embedded Component MODELWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上传时间： 2013-10-31
上传用户：jrsoft
IBIS 模型在做类似板级SI 仿真得到广泛应用。在做仿真的初级阶段，经常对于ibis 模型的描述有些疑问，只知道把模型拿来转换为软件所支持的格式或者直接使用，而对于IBIS 模型里面的数据描述什么都不算很明白，因此下面的一些描述是整理出来的一点对于ibis 的基本理解。在此引用很多presention来描述ibis 内容（有的照抄过来，阿弥陀佛，不要说抄袭，只不过习惯信手拈来说明一些问题），仅此向如muranyi 等ibis 先驱者致敬。本文难免有些错误或者考虑不周，随时欢迎进行讨论并对其进行修改！IBIS 模型的一些基本概念IBIS 这个词是Input/Output buffer information specification 的缩写。本文是基于IBIS ver3.2 所撰写出来（www.eigroup.org/IBIS/可下载到各种版本spec）,ver4.2增加很多新特性，由于在目前设计中没用到不予以讨论。。。在业界经常会把spice 模型描述为transistor MODEL 是因为它描述很多电路细节问题。而把ibis 模型描述为behavioral MODEL 是因为它并不象spice 模型那样描述电路的构成，IBIS 模型描述的只不过是电路的一种外在表现，象个黑匣子一样，输入什么然后就得到输出结果，而不需要了解里面驱动或者接收的电路构成。因此有所谓的garbage in, garbage out，ibis 模型的仿真精度依赖于模型的准确度以及考虑的worse case，因此无论你的模型如何精确而考虑的worse case 不周全或者你考虑的worse case 如何周全而模型不精确，都是得不到较好的仿真精度。
上传时间： 2013-10-16
上传用户：zhouli
IP核生成文件：（Xilinx/Altera 同） IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则asyn_fifo.veo 给出了例化该核方式（或者在 Edit－》Language Template-》COREGEN 中找到verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块，仿真时该文件也要加入工程。（在 ISE中点中该核，在对应的 processes 窗口中运行“ View Verilog Functional MODEL ”即可查看该 .v 文件）。如下图所示。
上传时间： 2013-10-20
上传用户：lingfei
AXI Bus Functional MODEL v1.1 Product Brief.pdf
上传时间： 2015-01-01
上传用户：kbnswdifs
