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Logic

Logic是苹果公司开发的mac软件,能够在Mac上构建起一间功能完备的专业录音室,从灵感初现到最后的母带制作,足以满足你的一切所需。
  • Verilog and VHDL状态机设计

    Verilog and VHDL状态机设计,英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital Logic only one Logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.

    标签: Verilog VHDL and 状态

    上传时间: 2013-12-19

    上传用户:change0329

  • The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services.

    The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals: To support massive concurrency, on the order of tens of thousands of clients per node To exhibit robust performance under wide variations in load and, To simplify the design of complex Internet services. SEDA decomposes a complex, event-driven application into a set of stages connected by queues. This design avoids the high overhead associated with thread-based concurrency models, and decouples event and thread scheduling from application Logic. SEDA enables services to be well-conditioned to load, preventing resources from being overcommitted when demand exceeds service capacity. Decomposing services into a set of stages also enables modularity and code reuse, as well as the development of debugging tools for complex event-driven applications.

    标签: Event-Driven Architecture Internet building

    上传时间: 2015-09-28

    上传用户:日光微澜

  • This thorough, hands-on reference for database developers and administrators delivers expert guidanc

    This thorough, hands-on reference for database developers and administrators delivers expert guidance on sophisticated uses of Transact-SQL (T-SQL)¡ ª one of the most familiar and powerful programming languages for SQL Server. Written by a T-SQL guru, this guide focuses on language features and how they are interpreted and processed by the SQL Server execution engine. You¡ ¯ ll get in-depth coverage of the sophisticated uses of T-SQL, including triggers, user-defined functions, exception handling, and more. The book explains and compares solutions to database-development problems in both SQL Server 2000 and SQL Server 2005, discussing the new T-SQL programming features added to SQL Server 2005 in detail. Includes extensive code samples, table examples, and Logic puzzles to help database developers and administrators understand the intricacies and help promote mastery of T-SQL.

    标签: administrators developers reference thorough

    上传时间: 2013-12-29

    上传用户:Avoid98

  • C++/CLI in Action is a practical guide that will help you breathe new life into your legacy C++ prog

    C++/CLI in Action is a practical guide that will help you breathe new life into your legacy C++ programs. The book begins with a concise C++/CLI tutorial. It then quickly moves to the key themes of native/managed code interop and mixed-mode programming. You抣l learn to take advantage of GUI frameworks like Windows Forms and WPF while keeping your native C++ business Logic. The book also covers methods for accessing C# or VB.NET components and libraries. Written for readers with a working knowledge of C++.

    标签: practical breathe Action legacy

    上传时间: 2015-10-17

    上传用户:wendy15

  • The present document specifies the CAMEL Application Part (CAP) supporting the fourth phase of the n

    The present document specifies the CAMEL Application Part (CAP) supporting the fourth phase of the network feature Customized Applications for Mobile network Enhanced Logic. CAP is based on a sub-set of the ETSI Core INAP CS-2 as specified by ETSI EN 301 140 1 [26]. Descriptions and definitions provided by ETSI EN 301 140 1 [26] are directly referenced by this standard in the case no additions or clarifications are needed for the use in the CAP.

    标签: the Application supporting specifies

    上传时间: 2015-12-24

    上传用户:84425894

  • This cookbook contains a wealth of solutions to problems that SQL programmers face all the time. Rec

    This cookbook contains a wealth of solutions to problems that SQL programmers face all the time. Recipes inside range from how to perform simple tasks, like importing external data, to ways of handling issues that are more complicated, like set algebra. Each recipe includes a discussion that explains the Logic and concepts underlying the solution. The book covers audit logging, hierarchies, importing data, sets, statistics, temporal data, and data structures.

    标签: programmers solutions cookbook contains

    上传时间: 2013-12-08

    上传用户:Altman

  • The jxcell allows any Java developer to automate any manual spreadsheet process within their organiz

    The jxcell allows any Java developer to automate any manual spreadsheet process within their organization. Automate the delivery of Excel reports and give your users the data they need in the format they want. Web-enable your existing spreadsheet business Logic as a scalable server-side calculation engine. embed Excel-compatible grids in applets and applications to automate spreadsheet data entry processes. enables you to integrate Excel-compatible spreadsheet functionality in your Windows applications without relying on Excel or writing VBA code.

    标签: spreadsheet any developer automate

    上传时间: 2016-04-29

    上传用户:xsnjzljj

  • vhdl编写

    vhdl编写,8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all Logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all Logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later

    标签: vhdl 编写

    上传时间: 2016-05-05

    上传用户:gundamwzc

  • CPU设计中的controlunit源码

    CPU设计中的controlunit源码,其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。

    标签: controlunit CPU 源码

    上传时间: 2016-05-25

    上传用户:com1com2

  • This file contains a selection of VHDL source files which serve to illustrate the diversity and powe

    This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic Logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools.

    标签: illustrate diversity selection contains

    上传时间: 2016-06-06

    上传用户:yimoney