Radio Frequency Integrated Circuit Design I enjoyed reading this book for a number of reasons. One reason is that itaddresses high-speed analog design in the context of microwave issues. This isan advanced-level book, which should follow courses in basic circuits andtransmission Lines. Most analog integrated circuit designers in the past workedon applications at low enough frequency that microwave issues did not arise.As a consequence, they were adept at lumped parameter circuits and often notcomfortable with circuits where waves travel in space. However, in order todesign radio frequency (RF) communications integrated circuits (IC) in thegigahertz range, one must deal with transmission Lines at chip interfaces andwhere interconnections on chip are far apart. Also, impedance matching isaddressed, which is a topic that arises most often in microwave circuits. In mycareer, there has been a gap in comprehension between analog low-frequencydesigners and microwave designers. Often, similar issues were dealt with in twodifferent languages. Although this book is more firmly based in lumped-elementanalog circuit design, it is nice to see that microwave knowledge is brought inwhere necessary.Too many analog circuit books in the past have concentrated first on thecircuit side rather than on basic theory behind their application in communications.The circuits usually used have evolved through experience, without asatisfying intellectual theme in describing them. Why a given circuit works bestcan be subtle, and often these circuits are chosen only through experience. Forthis reason, I am happy that the book begins first with topics that require anintellectual approach—noise, linearity and filtering, and technology issues. Iam particularly happy with how linearity is introduced (power series). In therest of the book it is then shown, with specific circuits and numerical examples,how linearity and noise issues arise.
上传时间： 2014-12-23
上传用户：han_zh
第一章 传输线理论一 传输线原理二 微带传输线三 微带传输线之不连续分析第二章 被动组件之电感设计与分析一 电感原理二 电感结构与分析三 电感设计与模拟四 电感分析与量测传输线理论与传统电路学之最大不同，主要在于组件之尺寸与传导电波之波长的比值。当组件尺寸远小于传输线之电波波长时，传统的电路学理论才可以使用，一般以传输波长（Guide wavelength）的二十分之ㄧ（λ/20）为最大尺寸，称为集总组件（Lumped elements）；反之，若组件的尺寸接近传输波长，由于组件上不同位置之电压或电流的大小与相位均可能不相同，因而称为散布式组件（Distributed elements）。 由于通讯应用的频率越来越高，相对的传输波长也越来越小，要使电路之设计完全由集总组件所构成变得越来越难以实现，因此，运用散布式组件设计电路也成为无法避免的选择。 当然，科技的进步已经使得集总组件的制作变得越来越小，例如运用半导体制程、高介电材质之低温共烧陶瓷（LTCC）、微机电（MicroElectroMechanical Systems, MEMS）等技术制作集总组件，然而，其中电路之分析与设计能不乏运用到散布式传输线的理论，如微带线（Microstrip Lines）、夹心带线（Strip Lines）等的理论。因此，本章以讨论散布式传输线的理论开始，进而以微带传输线为例介绍其理论与公式，并讨论微带传输线之各种不连续之电路，以作为后续章节之被动组件的运用。
标签： 传输线
上传时间： 2014-01-10
上传用户：sunshie
Calculation of the Differential Impedance of Tracks on FR4 substrates There is a discrepancy between calculated and measured values of impedance for differential transmission Lineson FR4. This is especially noticeable in the case of surface microstrip configurations. The anomaly is shown tobe due to the nature of the substrate material. This needs to be considered as a layered structure of epoxy resinand glass fibre. Calculations, using Boundary Element field methods, show that the distribution of the electricfield within this layered structure determines the apparent dielectric constant and therefore affects theimpedance. Thus FR4 cannot be considered to be uniform dielectric when calculating differential impedance.
上传时间： 2014-12-24
上传用户：DE2542
What would happen if someone connected 24V to your12V circuits? If the power and ground Lines were inadvertentlyreversed, would the circuits survive? Does yourapplication reside in a harsh environment, where the inputsupply can ring very high or even below ground? Evenif these events are unlikely, it only takes one to destroya circuit board.
上传时间： 2013-10-26
上传用户：jackandlee
单片机作为一种微型计算机，其内部具有一定的存储单元（8031除外），但由于其内部存储单元及端口有限，很多情况下难以满足实际需求。为此介绍一种新的扩展方法，将数据线与地址线合并使用，通过软件控制的方法实现数据线与地址线功能的分时转换，数据线不仅用于传送数据信号，还可作为地址线、控制线，用于传送地址信号和控制信号，从而实现单片机与存储器件的有效连接。以单片机片外256KB数据存储空间的扩展为例，通过该扩展方法，仅用10个I/O端口便可实现，与传统的扩展方法相比，可节约8个I/O端口。 Abstract: As a micro-computer,the SCM internal memory has a certain units(except8031),but because of its internal storage units and the ports are limited,in many cases it can not meet the actual demand.So we introduced a new extension method,the data line and address Lines combined through software-controlled approach to realize the time-conversion functions of data Lines and address Lines,so the data Lines not only transmited data signals,but also served as address Lines and control Lines to transmit address signals and control signals,in order to achieve an effective connection of microcontroller and memory chips.Take microcontroller chip with256KB of data storage space expansion as example,through this extension method,with only10I/O ports it was achieved,compared with the traditional extension methods,this method saves8I/O ports.
上传时间： 2014-12-26
上传用户：adada
1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 Lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
上传时间： 2013-11-08
上传用户：laozhanshi111
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission Lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上传时间： 2013-10-13
上传用户：ytulpx
The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) Lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full array protection.
上传时间： 2013-11-15
上传用户：fklinran
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) Lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上传时间： 2013-11-21
上传用户：q123321
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) Lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
标签： translating Level 9517 PCA
上传时间： 2013-12-25
上传用户：wsf950131
