虫虫首页| 资源下载| 资源专辑| 精品软件
登录| 注册

Limited

  • 基于单DSP的VoIP模拟电话适配器研究与实现

    基于单DSP的VoIP模拟电话适配器研究与实现:提出和实现了一种新颖的基于单个通用数字信号处理器(DSP)的VoIP模拟电话适配器方案。DSP的I/O和存储资源非常有限,通常适于运算密集型应用,不适宜控制密集型应用[5]。该系统高效利用单DSP的I/O和片内外存储器资源,采用μC/OS-II嵌入式实时操作系统,支持SIP和TCP-UDP/IP协议,通过LAN或者宽带接入,使普通电话机成为Internet终端,实现IP电话。该系统软硬件结构紧凑高效,运行稳定,成本低,具有广阔的应用前景。关键词:模拟电话适配器;IP电话;数字信号处理器;μC/OS-II 【Abstract】This paper presents a VoIP ATA solution based on a single digital signal processor (DSP). DSPs are suitable for arithmetic-intensiveapplication and unsuitable for control-intensive application because of the limitation of I/O and memory resources. This solution is based on a 16-bitfixed-point DSP and μC/OS-II embedded real-time operating system. It makes good use of the Limited resources, supports SIP and TCP-UDP/IPprotocol. It can connect the analog telephone to Internet and realize the VoIP application. This system has a great future for its high efficiency andlow cost.【Key words】Analog telephone adapter (ATA); Voice over Internet protocol (VoIP); Digital signal processor (DSP); μC/OS-II Research and Implementation of VoIPATA Based on Single DSP

    标签: VoIP DSP 模拟电话 适配器

    上传时间: 2013-11-20

    上传用户:Wwill

  • 为您的FPGA选择合适的电源

    Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not Limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.

    标签: FPGA 电源

    上传时间: 2013-11-10

    上传用户:iswlkje

  • Virtex-6 FPGA PCB设计手册

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not Limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    标签: Virtex FPGA PCB 设计手册

    上传时间: 2014-01-13

    上传用户:竺羽翎2222

  • CPLD库指南

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not Limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.  

    标签: CPLD

    上传时间: 2013-10-22

    上传用户:李哈哈哈

  • 基于码本映射的语音带宽扩展算法研究

    在现代通信系统中,电话语音的频带被限制在300 Hz~4 kHz的范围内,带来了语音可懂度和自然度的降低。为了在不增加额外成本的前提下提高语音的可懂度和自然度,进行了电话语音频带扩展的研究。提出了一种改进的基于码本映射的语音带宽扩展算法:在码本映射的过程中,使用加权系数来得到映射码本。客观测试结果表明,用此算法得到的宽带语音的谱失真度比用一般的码本映射降低至少2%。主观测试结果表明,用此算法得到的宽带语音具有更好的可懂度和自然度。 Abstract:  In modern communication systems, the bandwidth of telephone speech is Limited from 300Hz to 4 kHz, which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness, without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping, weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%, comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.

    标签: 映射 带宽 扩展 语音

    上传时间: 2014-12-29

    上传用户:15501536189

  • Virtex-6 FPGA PCB设计手册

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not Limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    标签: Virtex FPGA PCB 设计手册

    上传时间: 2013-11-11

    上传用户:zwei41

  • CPLD库指南

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not Limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.  

    标签: CPLD

    上传时间: 2014-12-05

    上传用户:qazxsw

  • 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in

    关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is Limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    标签: investigates implementing pipelines circuits

    上传时间: 2015-07-26

    上传用户:CHINA526

  • Design Specification Introduction Goals and Objectives GameForge is a graphical tool used

    Design Specification Introduction Goals and Objectives GameForge is a graphical tool used to aid in the design and creation of video games. It attempts to bring game development down to a level that any computer savvy user can understand, without requiring masterful programming ability. A user with Limited Microsoft DirectX and/or Visual C++ programming knowledge will be able to construct a basic, 2-D arcade game. GameForge limits the amount of actual code written by the user, if not eliminating it completely. It will also assist experienced programmers in generating the Microsoft DirectX and Microsoft Windows9x overhead necessary for basic game construction, allowing them to concentrate on more detailed game design issues and implementation.

    标签: Specification Introduction Objectives GameForge

    上传时间: 2013-12-27

    上传用户:wl9454

  • 最优化算法

    最优化算法,应用有限内存拟牛顿方法(Limited Memory (variable-storage)quasi-Newton method)求解高维最优化问题,使用更多的内存将使算法更有效。

    标签: 优化算法

    上传时间: 2015-08-08

    上传用户:cuiyashuo