基于USB接口的数据采集模块的设计与实现Design and Implementation of USB-Based Data Acquisition Module路 永 伸(天津科技大学电子信息与自动化学院，天津300222)摘要文中给出基于USB接口的数据采集模块的设计与实现。硬件设计采用以Adpc831与PDIUSBDI2为主的器件进行硬件设计，采用Windriver开发USB驱动，并用Visual C十十6.0对主机软件中硬件接口操作部分进行动态链接库封装。关键词USB 数据采集Adpc831 PDNSBDI2 Windriver动态链接库Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTUSBD12i sused for hardware design. The USB drive is developed场Wmdriver, and the operation on the hardware InterfACe is packaged into Dynamic Link Libraries场Visual C++6.0. Keywords USB DataA cquisition Adttc831 PDfUSBD12 Windriver0 引言US B总 线 是新一代接口总线，最初推出的目的是为了统一取代PC机的各类外设接口，迄今经历了1.0,1.1与2.0版本3个标准。在国内基于USB总线的相关设计与开发也得到了快速的发展，很多设计者从各自的应用领域，用不同方案设计出了相应的装置[1,2]。数据采集是工业控制中一个普遍而重要的环节，因此开发基于USB接口的数据采集模块具有很强的现实应用意义。虽然 US B总线标准已经发展到2.0版本，但由于工业控制现场干扰信号的情况比较复杂，高速数据传输的可靠性不容易被保证，并且很多场合对数据采集的实时性要求并不高，开发2.0标准产品的成本又较1.1标准产品高，所以笔者认为，在工业控制领域，目前开发基于USB总线1.1标准实现的数据采集模块的实用意义大于相应2.0标准模块。
上传时间： 2013-10-23
上传用户：q3290766
Abstract: Designers who must InterfACe 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
标签： PicoBlaze Create Master Xilinx
上传时间： 2013-11-05
上传用户：a6697238
This application note describes how to implement the Bus LVDS (BLVDS) InterfACe in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
标签： Implementing LVDS 522 Bus
上传时间： 2013-11-10
上传用户：frank1234
This application note explains the XC9500™/XL/XV Boundary Scan InterfACe anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the iMPACT software operations and provides an overview of theadditional operations supported by XC9500/XL/XV CPLDs for in-system programming.
上传时间： 2013-11-15
上传用户：fengweihao158@163.com
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG InterfACe using theEmbedded JTAG ACE Player.
上传时间： 2013-11-14
上传用户：JIMMYCB001
The PLB BRAM InterfACe Controller is a module thatattaches to the PLB (Processor Local Bus).
上传时间： 2013-10-27
上传用户：zoudejile
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O InterfACe. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间： 2013-10-22
上传用户：liu999666
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible InterfACe (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display InterfACe on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to InterfACe with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-19
上传用户：yyyyyyyyyy
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven InterfACe allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial InterfACe with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-23
上传用户：leyesome
