This document is a quick reference to some of the formulas and important INformation related to optical technologies. It focuses on decibels (dB), decibels per milliwatt (dBm), attenuation and measurements, and provides an introduction to optical fibers.
上传时间： 2013-10-17
上传用户：libenshu01
同步技术是跳频通信系统的关键技术之一，尤其是在快速跳频通信系统中，常规跳频通信通过同步字头携带相关码的方法来实现同步，但对于快跳频来说，由于是一跳或者多跳传输一个调制符号，难以携带相关码。对此引入双跳频图案方法，提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息，克服了快速跳频难以携带相关码的困难。分析了同步性能，仿真结果表明该方案同步时间短、虚警概率低、捕获概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization INformation， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization INformation is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
上传时间： 2013-11-23
上传用户：mpquest
The INformation in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
标签： 技术资料
上传时间： 2013-10-08
上传用户：stewart·
This book contains INformation obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and INformation, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use.
上传时间： 2014-12-31
上传用户：PresidentHuang
飞思卡尔智能车的舵机测试程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative INformation */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //锁相环电路允许位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵机初始化 PWMCTL_CON01=1; //0和1联合成16位PWM； PWMCAE_CAE1=0; //选择输出模式为左对齐输出模式 PWMCNT01 = 0; //计数器清零； PWMPOL_PPOL1=1; //先输出高电平，计数到DTY时，反转电平 PWMPRCLK = 0X40; //clockA 不分频,clockA=busclock=16MHz;CLK B 16分频:1Mhz PWMSCLA = 0x08; //对clock SA 16分频,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //选择clock SA做时钟源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高电平时间为1.5ms; PWME_PWME1 = 1;
上传时间： 2013-11-04
上传用户：狗日的日子
IBIS 模型在做类似板级SI 仿真得到广泛应用。在做仿真的初级阶段，经常对于ibis 模型的描述有些疑问，只知道把模型拿来转换为软件所支持的格式或者直接使用，而对于IBIS 模型里面的数据描述什么都不算很明白，因此下面的一些描述是整理出来的一点对于ibis 的基本理解。在此引用很多presention来描述ibis 内容（有的照抄过来，阿弥陀佛，不要说抄袭，只不过习惯信手拈来说明一些问题），仅此向如muranyi 等ibis 先驱者致敬。本文难免有些错误或者考虑不周，随时欢迎进行讨论并对其进行修改！IBIS 模型的一些基本概念IBIS 这个词是Input/Output buffer INformation specification 的缩写。本文是基于IBIS ver3.2 所撰写出来（www.eigroup.org/IBIS/可下载到各种版本spec）,ver4.2增加很多新特性，由于在目前设计中没用到不予以讨论。。。在业界经常会把spice 模型描述为transistor model 是因为它描述很多电路细节问题。而把ibis 模型描述为behavioral model 是因为它并不象spice 模型那样描述电路的构成，IBIS 模型描述的只不过是电路的一种外在表现，象个黑匣子一样，输入什么然后就得到输出结果，而不需要了解里面驱动或者接收的电路构成。因此有所谓的garbage in, garbage out，ibis 模型的仿真精度依赖于模型的准确度以及考虑的worse case，因此无论你的模型如何精确而考虑的worse case 不周全或者你考虑的worse case 如何周全而模型不精确，都是得不到较好的仿真精度。
上传时间： 2013-10-16
上传用户：zhouli
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more INformation on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-05
上传用户：超凡大师
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For INformation on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
上传时间： 2015-01-02
上传用户：时代将军
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This INformation can be usedfor partial reconfiguration or partial readback.
上传时间： 2013-11-16
上传用户：qingdou
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides INformation on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
标签： Spartan-XL Express XAPP FPGA
上传时间： 2015-01-02
上传用户：nanxia
