All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.
上传时间： 2013-11-10
上传用户：liaofamous
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上传时间： 2013-11-19
上传用户：shirleyYim
//芯片资料请到www.elecfans.com查找 //DS1820 C51 子程序//这里以11.0592M晶体为例，不同的晶体速度可能需要调整延时的时间//sbit DQ =P2^1;//根据实际情况定义端口 typedef unsigned char byte;typedef unsigned int word; //延时void delay(word useconds){ for(;useconds>0;useconds--);} //复位byte ow_reset(void){ byte presence; DQ = 0; //pull DQ line low delay(29); // leave it low for 480us DQ = 1; // allow line to return high delay(3); // wait for presence presence = DQ; // get presence signal delay(25); // wait for end of timeslot return(presence); // presence signal returned} // 0=presence, 1 = no part //从 1-wire 总线上读取一个字节byte read_byte(void){ byte i; byte value = 0; for (i=8;i>0;i--) { value>>=1; DQ = 0; // pull DQ low to start timeslot DQ = 1; // then return high delay(1); //for (i=0; i<3; i++); if(DQ)value|=0x80; delay(6); // wait for rest of timeslot } return(value);} //向 1-WIRE 总线上写一个字节void write_byte(char val){ byte i; for (i=8; i>0; i--) // writes byte, one bit at a time { DQ = 0; // pull DQ low to start timeslot DQ = val&0x01; delay(5); // hold value for remainder of timeslot DQ = 1; val=val/2; } delay(5);} //读取温度char Read_Temperature(void){ union{ byte c[2]; int x; }temp; ow_reset(); write_byte(0xCC); // Skip ROM write_byte(0xBE); // Read Scratch Pad temp.c[1]=read_byte(); temp.c[0]=read_byte(); ow_reset(); write_byte(0xCC); //Skip ROM write_byte(0x44); // Start Conversion return temp.x/2;}
上传时间： 2013-11-03
上传用户：hongmo
//遥控解码子程序，LC7461，用户码为11C//external interrupt0void isr_4(){ unsigned char r_count;//定义解码的个数 unsigned long use_data=0;//定义16位的用户码，只用到13位 unsigned long use_code=0;//定义16位的用户反码，只用到13位 unsigned long data=0;//定义16位数据码，包括8位数据码和反码 unsigned char data_h=0;//数据反码 unsigned char data_l=0;//数据码 _clrwdt();// _delay(7000);//7461解码，延时7000// _delay(7000);//7461解码，延时7000//_delay(7000);//7461解码，延时7000 if(remote==1) goto error; while(remote==0);//wait to high //_delay(9744);count_delay=0; while(count_delay<143); if(remote==1) goto error; /////用户码解码use_data//////////add////////////////////////// for(r_count=13;r_count>0;r_count--) { while(remote==0);//wait to high count_delay=0; while(count_delay<24);//_delay(1680); _c=remote; if(_c==1) { _lrrc(&use_data); count_delay=0; while(count_delay<32);//_delay(2200);//wait to low } else _lrrc(&use_data); } _nop(); //if(remote==1) //_delay(1680);//wait to low while(remote==1);//wait to low _nop(); ////////用户码解码finish/////////add/////////add//////// /////用户码反码解码use_code//////////add////////////////////////// for(r_count=13;r_count>0;r_count--) { while(remote==0);//wait to high count_delay=0; while(count_delay<24);//_delay(1680); _c=remote; if(_c==1) { _lrrc(&use_code); count_delay=0; while(count_delay<32);//_delay(2200);//wait to low } else _lrrc(&use_code); } _nop(); //if(remote==1) // _delay(1680);//wait to low while(remote==1);//wait to low _nop(); ////////用户码反码解码finish/////////add/////////add//////// ////数据码解码开始////data_l为用户码，data_h为数据码反码//////////// for(r_count=16;r_count>0;r_count--) { while(remote==0);//wait to high count_delay=0; while(count_delay<24);//_delay(1680); _c=remote; if(_c==1) { _lrrc(&data); count_delay=0; while(count_delay<32);//_delay(2200);//wait to low } else _lrrc(&data); } ////数据码解码结束//////////////////////////////////////////////// data_l=data; data_h=data>>8; ///用户码////// use_data>>=3; use_code>>=3; use_code=~use_code; //////// ////如果用户码等与0x11c并且数据码和数据反码都校验一致，解码成功 //if((~data_h==data_l)&&use_data==0x11c)//使用用户码 //跳过用户码 if(~data_h==data_l)//如果数据码和数据反码（取反后）相等，解码正确 { _nop(); r_data=data_l;//r_data为解出的最终数据码 } //否则解码不成功 _nop(); _nop();error: //r_data=nocode; _nop(); _nop(); _nop();}
上传时间： 2014-03-27
上传用户：shenlan
基于多点网络的水厂自动监控系统设计Design of MPI Based Automatic Monitoring and Control System in Water Works刘 美 俊(湖南工程学院，湘潭411101)摘要针对水厂工作水泵多、现场离控制站距离远的特点，提出了一种基于MPI多点网络的自动监控系统的设计方法，分析了系统的工作原理，介绍了系统中数据的采集与处理、主站与从站的通信原理以及系统软件的设计。由于这种系统的主、从站PLC之间采用MPI网络通信，具有运行可靠、性能价格比高的特点，所以适用于中小规模水厂的分布式监控场合。关键词多点网络主站从站监控系统Abstract Ina ccordancew ithth efe atuersof w aterw orks,i. e. ，manyp umpsin o perationa ndth ep umps， farfor mt hec ontrolst ation,th em ethodo fdesigninga na utomati(〕monitoringa ndc ontorlsy stemb asedo nM PIis p resented.Th eo perationalpr incipleo fth esy stemi san alyzed,th ed atac olection,data processing; communication between master station and slave station as wel as design and system software are discussed. Because MPI network communicationis used among master station, slave stations and PLC, the system is reliable and high cost-efective. It is， suitable for smal and mediumsized water works for distrbuted monitoring and control.Keywords MPI Masterst ation Slaves tation Monitoringa ndc ontorlsy stem 自来 水 厂 的自动控制系统一般分为两大部分，一对组态硬件要求较高，投资较大。相对而言，MPI网是水源地深水泵的工作控制，一是水厂区变频恒压供络速度可达187.5 M bps，通过一级中继器传输距离可水控制，两部分的实际距离通常都比较远。某厂水源达Ikm 。根据水厂的具体情况，确定以MPI方式组地有3台深井泵给水厂区的蓄水池供水。水厂区的成网络，主站PLC为S7-300系列的CPU3121FM，从任务是对水池的水进行消毒处理后，通过加压泵向管站为S7-200系列的CPU222。这样既满足了系统要路恒压供水。选用Siemens公司的S7系列可编程控求，又相对于Profibus网络节省了三分之一的成本，制器(PLC)和上位机组成实时数据采集和监控系统， 这种分布式监控系统具有较高的性能价格比。系统对深水泵进行远程控制，对供水泵采用变频器进行恒中PLC的物理层采用RS - 485接口，网络延伸选用压控制以保证整个水厂的电机设备安全、可靠地运带防雷保护的中继器，使系统的安全运行得到了保行。证。MPI网络的拓扑结构如图1所示。1 多点网络(NWI)监控系统的组成Sie me ns 公司S7系列PLC通常有MP」多点网络与Profibus现场总线网络两种组网方式。Profibus现场总线的应用目前较为普遍，通用性较好，它由Profibus一DP, Profibus一FMS, Profibus一PA组成。Profibus - DP型用于分散外设间的数据传输，传输速率为9.6kbps一12Mbps，主要用于现场控制器与分散1/0之间的通信，可满足交直流调速系统快速响应的时间要求，特别适合于加工自动化领域的应用;Profibus - FMS主要解决车间级通信问题，完成中等传输速度的循环或非循环数据交换任务，适用于纺织、楼宇自动化、可编程控制器、低压开关等;Profibus - PA型采用了OSI模型的物理层和数据链路层，适用于过程自动化的总线类型。
上传时间： 2013-10-09
上传用户：fac1003
基于变频调速的水平连铸机拉坯辊速度控制系统Frequency Inverter Based Drawing RollerS peedC ontrolSy stem ofHorizontal Continuous Casting MachineA 伟刘冲旅巴(南 华 大 学电气工程学院，衡阳421001)摘要拉坯辊速度控制是水平连铸工艺的关键技术之一，采用变频器实现水平连铸机拉坯辊速度程序控制，由信号发生装置给变频器提供程控信号。现场应用表明该控制系统速度响应快，控制精度高，满足了水平连铸生产的需要。关键词水平连铸拉坯辊速度程序控制变频器Absh'act Speedc ontorlof dr awingor leris on eo fth ek eyte chnologiesfo rho rizontalco ntinuousca stingm achine.Fo rth ispu rpose,fr equencyco nverterisad optedfo rdr awingor lersp eedp rogrammablec ontorlof ho rizontalco ntinuousca stingm achine,th ep rogrammableco ntorlsi gnalto fr equencyc onverteris provided场a signal generator. The results of application show that the response of system is rapid and the control accuracy is high enough to meet thedemand of production of horizontal continuous casting.Keywords Horizontalco ntinuousc asting Drawingor ler Speedp rogrammablec ontrol Ferquencyin verter 随着 现 代 化工业生产对钢材需求量的日益增加，连铸生产能力已经成为衡量一个国家冶金工业发展水平的重要指标之一。近十几年来，水平连铸由于具有投资少、铸坯直、见效快等多方面的优点，国内许多钢铁企业利用水平连铸机来浇铸特种合金钢，发挥了其独特的优势并取得了较好的经济效益〔1,2)0采用 水 平 连铸机浇铸特种合金钢时，由于拉坯机是水平连铸系统中的关键设备之一，拉坯机及其控制性能的好坏直接影响着连铸坯的质量，因此，连铸的拉坯技术便成为整个水平连铸技术的核心。由于钢的冶炼过程是在高温下进行的，钢水温度的变化又容易影响铸坯的质量和成材率，因此，如何能在高温环境下控制好与铸坯速度相关的参数(拉、推程量，中停时间和拉坯频率等)对于确保连铸作业的进一步高效化，延长系统的连续作业时间十分关键。因此，拉坯辊速度控制技术是连铸生产过程控制领域中的关键技术之- [31
上传时间： 2013-10-12
上传用户：gxy670166755
摘 要:用一种新的思路和方法,先计算低通、再计算高通滤波器的有关参数,然后组合成带通滤波器.关键词:滤波器;参数;新思路中图分类号: TN713. 5 文献识别码:B 文章编号:1008 - 1666 (1999) 04 - 0089 - 03A New Consideration of the Band Filter’s CalculationGuo Wencheng( S hao Yang B usiness and Technology school , S haoyang , Hunan ,422000 )Abstract :This essay deals with a new method of calculating the band filters - first calculatingthe relevant parameters of low - pass filters ,then calculating the ones of high - pass filters.Key words :filter ; parameters ;new considercation八十年代后,信息产业得到了迅猛发展. 带通滤波器在微波通信、广播电视和精密仪器设备中得到了广泛应用. 带通滤波器性能的优劣,对提高接收机信噪比,防止邻近信道干扰,提高设备的技术指标,有着十分重要的意义.我在长期的教学实践中,用切比雪夫型方法设计、计算出宽带滤波器集中参数元件的数据. 该滤波器可运用在检测微波频率的仪器和其他设备中. 再将其思路和计算方法介绍给大家,供参考.
上传时间： 2014-12-28
上传用户：Yukiseop
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上传时间： 2013-11-10
上传用户：1427796291
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
