Introduce HIgh-speed Digital System Design.
标签： HIgh-speed Digital Design System
上传时间： 2013-10-20
上传用户：gps6888
The TJA1042 is a HIgh-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for HIgh-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
标签： HIgh-speed transce 1042 TJA
上传时间： 2014-12-28
上传用户：气温达上千万的
The TJA1051 is a HIgh-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for HIgh-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
标签： HIgh-speed transce 1051 TJA
上传时间： 2013-10-17
上传用户：jisujeke
FlexCompress is a HIgh-speed compression library developed to provide archive functionality for your applications. This solution provides flexible compression and strong encryption algorithms that allows you to integrate archiving or backup features into your programs in a fast and easy way.
标签： functionality FlexCompress compression HIgh-speed
上传时间： 2015-04-04
上传用户：s363994250
Multicode HIgh-speed Transmission for Wireless Mobile Communications
标签： Communications Transmission HIgh-speed Multicode
上传时间： 2014-01-08
上传用户：GavinNeko
pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.
上传时间： 2014-01-22
上传用户：曹云鹏
HSDPA（High Speed Downlink Packet Access）技术是WCDMA基于R5的增强型技术，通过各种 核心技术可使下行速率达到14.4M，是WCDMA移动运营商进行大流量移动多媒体服务的首选技术。 下面简单介绍中兴通讯的HSPDA解决方案... ...
标签： Downlink Access Packet HSDPA
上传时间： 2015-05-13
上传用户：顶得柱
Interfacing AD7276 HIgh-speed Data Converters to ADSP-BF535 Blackfin Processors
标签： Interfacing HIgh-speed Converters Processors
上传时间： 2013-12-20
上传用户：希酱大魔王
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
标签： integrating controller guidelines document
上传时间： 2013-11-27
上传用户：电子世界
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
标签： integrating controller guidelines document
上传时间： 2015-11-18
上传用户：xhz1993
