Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
上传时间： 2013-10-14
上传用户：cxl274287265
Designing Boards with Atmel AT89C51, AT89C52, AT89C1051, and AT89C2051 for Writing Flash at In-Circuit Test:Recent improvements in chips andtesters have made it possible for thetester to begin taking over the role traditionallyassigned to the PROM programmer.Instead of having a PROM programmerwrite nonvolatile memoriesbefore assembling the board, the in-circuittester writes them during in-circuittesting operations. Many Teradyne Z18-series testers are now in use loadingcode into nonvolatile memories, microcontrollersand in-circuit programmable logic devices. The purpose of this note is to explain how the Z18 approaches the writing task for Atmel AT89C series IC’s,so that designers of boards using these chips can get the best results.
标签： Designing Boards Atmel with
上传时间： 2013-11-20
上传用户：lijianyu172
离散傅里叶变换,(DFT)Direct Fouriet Transformer(PPT课件) 一、序列分类对一个序列长度未加以任何限制，则一个序列可分为： 无限长序列：n=-∞~∞或n=0~∞或n=-∞~ 0 有限长序列：0≤n≤N-1有限长序列在数字信号处理是很重要的一种序列。由于计算机容量的限制，只能对过程进行逐段分析。二、DFT引入由于有限长序列，引入DFT(离散付里叶变换)。DFT它是反映了“有限长”这一特点的一种有用工具。DFT变换除了作为有限长序列的一种付里叶表示，在理论上重要之外，而且由于存在着计算机DFT的有效快速算法--FFT,因而使离散付里叶变换(DFT)得以实现，它使DFT在各种数字信号处理的算法中起着核心的作用。三、本章主要讨论 离散付里叶变换的推导离散付里叶变换的有关性质离散付里叶变换逼近连续时间信号的问题第二节 付里叶变换的几种形式傅 里 叶 变 换 ： 建 立 以 时 间 t 为 自 变 量 的 “ 信 号 ” 与 以 频 率 f为 自 变 量 的 “ 频 率 函 数 ”(频谱) 之 间 的 某 种 变 换 关 系 . 所 以 “ 时 间 ” 或 “ 频 率 ” 取 连 续 还 是 离 散 值 , 就 形 成 各 种 不 同 形 式 的 傅 里 叶 变 换 对 。, 在 深 入 讨 论 离 散 傅 里 叶 变 换 D F T 之 前 , 先 概 述 四种 不 同 形式 的 傅 里 叶 变 换 对 . 一、四种不同傅里叶变换对傅 里 叶 级 数(FS)：连 续 时 间 , 离 散 频 率 的 傅 里 叶 变 换 。连 续 傅 里 叶 变 换(FT)：连 续 时 间 , 连 续 频 率 的 傅 里 叶 变 换 。序 列 的 傅 里 叶 变 换(DTFT):离 散 时 间 , 连 续 频 率 的 傅 里 叶 变 换.离 散 傅 里 叶 变 换(DFT):离 散 时 间 , 离 散 频 率 的 傅 里 叶 变 换1.傅 里 叶 级 数(FS)周期连续时间信号 非周期离散频谱密度函数。 周期为Tp的周期性连续时间函数 x(t) 可展成傅里叶级数X(jkΩ0) ,是离散非周期性频谱 , 表 示为:例子通过以下 变 换 对 可 以 看 出 时 域 的 连 续 函 数 造 成 频 域 是 非 周 期 的 频 谱 函 数 , 而 频 域 的 离 散 频 谱 就 与 时 域 的 周 期 时 间 函 数 对 应 . (频域采样，时域周期延 拓)2.连 续 傅 里 叶 变 换(FT)非周期连续时间信号通过连续付里叶变换(FT)得到非周期连续频谱密度函数。
上传时间： 2013-11-19
上传用户：fujiura
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
标签： USR_ACCESS PowerPC XAPP 719
上传时间： 2013-11-13
上传用户：我累个乖乖
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-19
上传用户：yyyyyyyyyy
本文主要通过介绍PLC通讯的意义和三菱FX系列PLC的四种通讯方式，并重点介绍FX系列PLC与计算机无协议通讯，主要从无协议通讯的硬件、配线、数据寄存器设置、PLC与计算机无协议通讯的指令用法、PLC程序编写和计算机VB程序的编写来说明无协议通讯的过程和一般方法。 My dissertation introduces the significance of PLC communications and the four means of communication of Mitsubishi FX’s PLC, And highlights the no protocol communications of FX series PLC and computer, no protocol communications hardware, wiring, Register data set, and the usage of command about no protocol communications, How to write PLC program and computer VB program to illustrate the process of no protocol communications and general method.
上传时间： 2014-11-29
上传用户：Jerry_Chow
ARM is the world’s leading semiconductor IP company with 22 Million processors entering the market each day.
标签： Development_FSL Embedded Kinetis Series
上传时间： 2013-11-01
上传用户：kaixinxin196
