空时正交编码源程序，参考文献： V.Tarokh,H. Jafarkhani,and A. R. Calderbank "Space-Time Codes from ％Orthogonal Designs",IEEE Trans. Inform. Theory VOL. 45,NO. 5,JULY 1
上传时间： 2013-12-26
上传用户：fandeshun
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real Designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of Designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software engineering
标签： transportation engineering documents including
上传时间： 2015-08-15
上传用户：lixinxiang
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of Designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software
标签： transportation engineering documents including
上传时间： 2013-12-26
上传用户：Zxcvbnm
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of Designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java
标签： transportation engineering documents including
上传时间： 2015-08-15
上传用户：caixiaoxu26
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of Designs documents, made the comprehensive analysis to the public transportation systems engineering to
标签： transportation engineering documents including
上传时间： 2015-08-15
上传用户：时代电子小智
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of Designs documents, made the comprehensive analysis
标签： transportation engineering documents including
上传时间： 2014-01-07
上传用户：saharawalker
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of Designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
标签： Technology simulation simulator the
上传时间： 2013-12-26
上传用户：zl5712176
Integration的EZMac Lite，对于开发IA4420/4421很有用！ Fixed packet length protocol MAC layer for simplifying EZRadio Designs.
标签： Integration EZMac Lite
上传时间： 2014-01-27
上传用户：曹云鹏
Integration的EZMac Plus，对于开发IA4420/4421很有用！ Variable packet length protocol with packet forwarding capability MAC layer for simplifying EZRadio Designs
标签： Integration EZMac Plus
上传时间： 2016-05-12
上传用户：alan-ee
