基于单片机的汽车多功能报警系统设计The Design of Automobile Multi-function AlarmingBased on Single Chip Computer刘法治赵明富宁睡达(河 南 科 技 学 院 ，新 乡 453 00 3)摘要介绍了一种基于单片机控制的汽车多功能报警系统，它能对汽车的润滑系统油压、制动系统气压、冷却系统温度、轮胎欠压及防盗进行自动检测，并在发现异常情况时，发出声光报警。阐述了该报警系统的硬件组成及软件设计方法。关键词单片机传感器数模转换报警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly场thesystem. Audio and visual alarms wil be provided under abnormal conditions厂The hardware composition and software design of the system， Described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽车多功能报苦器硬件系统设计根据 系 统 实际需要和产品性价比，选用ATMEL公司新生产的采用CMOs工艺的低功耗、高性能8位单片机AT89S52作为系统的控制器。AT89S52的片内有8k Bytes LSP Flash闪烁存储器，可进行100(〕次写、擦除操作;256Bytes内部数据存储器(RAM);3 2 根可编程输N输出线;2个可编程全双工串行通道;看门狗(WTD)电路等。系统由传感器、单片机、模数转换器、无线信号发射电路、指示灯驱动电路、声光报警驱动电KD一9563，发出三声二闪光。并触发一个高电平，驱动无线信号发射电路。
上传时间： 2013-11-09
上传用户：gxmm
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design Described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上传时间： 2013-11-11
上传用户：zhouli
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are Described in detail, followed by detailed instructions thatshow how to implement the configuration circui
标签： Spartan-XL Express XAPP FPGA
上传时间： 2014-12-28
上传用户：hewenzhi
针对传统集成电路（ASIC）功能固定、升级困难等缺点，利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块，在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波，给出了DQPSK解调的原理和实现方法，推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序，在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, Described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上传时间： 2013-11-06
上传用户：liu123
This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts Described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
上传时间： 2013-10-29
上传用户：旭521
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like Described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上传时间： 2013-10-24
上传用户：s蓝莓汁
阐述了轨道交通列车定位技术。介绍了在轨道交通系统中列车定位技术的功能，国内外轨道交通中主要采用的列车定位方法，重点论述了几种主要定位技术，并从定位精度、闭塞制式、维护投资成本、抗干扰等方面进行分析比较。提出目前轨道交通定位技术应综合运用，取长补短，多种方法相互融合，才能满足轨道交通中对安全可靠性的要求。 Abstract: Rail train positioning technology is Described. The paper introduces the funetions of the train positioning technology in the rail transit system， the main methods of train positioning do mestic and international rail， and focuses on several key methods， analyzes and compares from the positioning accuracy， block system, maintenance and investment cost， interference and so on， suggested that the current rail positioning technology should be integrated use of positioning method of meriging， learn from each other， to meet the reliability requirements of rail safety.
上传时间： 2013-11-25
上传用户：franktu
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design Described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上传时间： 2013-10-09
上传用户：guojin_0704
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are Described in detail, followed by detailed instructions thatshow how to implement the configuration circui
标签： Spartan-XL Express XAPP FPGA
上传时间： 2015-01-02
上传用户：nanxia
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code Described in this document, go to sectionVHDL Code, page 5 for instructions.
标签： CoolRunner-II XAPP CPLD 380
上传时间： 2013-10-26
上传用户：kiklkook
