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ControlLER

  • The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i

    The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset ControlLER from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.

    标签: diffusion-limited-aggregation DLA generates 320x240

    上传时间: 2014-01-16

    上传用户:225588

  • ISCAS的benchmark 含有原理图

    ISCAS的benchmark 含有原理图,VHDL、VerilogHDL网表,测试数据等。 27-channel interrupt ControlLER

    标签: benchmark ISCAS 原理图

    上传时间: 2016-12-07

    上传用户:h886166

  • The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of dig

    The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of digital signal processor (DSP) ControlLERs, are part of the TMS320C2000 platform of fixed-point DSPs. The 240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP ControlLER. While code-compatible with the existing C24x DSP ControlLER devices, the 240xA offers increased processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary section for device-specific features.

    标签: TMS 320 generation 240

    上传时间: 2013-12-16

    上传用户:GavinNeko

  • DDR SDRAM控制器的VHDL源代码

    DDR SDRAM控制器的VHDL源代码,含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a ControlLER of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a ControlLER design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.

    标签: SDRAM VHDL DDR 控制器

    上传时间: 2014-11-01

    上传用户:l254587896

  • AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on k14 fw1.1) Windows CE Em

    AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on k14 fw1.1) Windows CE Embedded CE 6.0 driver installation. 1. Unzip the installation file onto your system (called installation directory below) 2. Create an OS design or open an existing OS design in Platform Builder 6.0. a. The OS must support the SD bus driver and have an SD Host ControlLER driver (add these from Catalog Items). b. Run image size should be set to allow greater than 32MB. 3. a. From the Project menu select Add Existing Subproject... b. select AR6K_DRV.pbxml c. select open This should create a subproject within your OS Design project for the AR6K_DRV driver. 4. Build the solution.

    标签: installation Windows Driver March

    上传时间: 2014-09-06

    上传用户:yuzsu

  • MPC8260-MCC-HOWTO Abstract: This document attempts to give the linux developer community of motoro

    MPC8260-MCC-HOWTO Abstract: This document attempts to give the linux developer community of motorola(R) s mpc8260 processor a fairly good idea of programming details of Multi Channel ControlLER. This document can be distributed under GPL version 2.0 or later, GPL is available at (http://www.gnu.org/copyleft/gpl.html)

    标签: MCC-HOWTO developer community Abstract

    上传时间: 2017-01-11

    上传用户:silenthink

  • 单片微型计算机是微型计算机发展中的一个重要分支

    单片微型计算机是微型计算机发展中的一个重要分支,是把构成一台微型计算机的主要部件如中央处理器(CPU)、存储器(RAM/ROM)和各种功能I/O接口集成在一块芯片上的单芯片微型计算机(Single Chip Micro Computer),简称单片机.由于它的结构与指令功能都是按工业控制要求设计的,且近年来单片机着力扩展了各种控制功能如A/D、PWM等,因此我们更多时候称其为一个单片形态的微控制器(Single Chip Micro ControlLER),或直接称其为微控制器(Micro ControlLER)。

    标签: 微型计算机 发展 分支

    上传时间: 2014-01-18

    上传用户:zhaoq123

  • 新加原版MemDev功能模块 UCGUI3.90版源码有如下几点新的变化. 1.这个版本的UCGUI提供了模拟器的源码[本站上似乎有3.24版的带模拟器源码的UCGUI下载, 大家比较一

    新加原版MemDev功能模块 UCGUI3.90版源码有如下几点新的变化. 1.这个版本的UCGUI提供了模拟器的源码[本站上似乎有3.24版的带模拟器源码的UCGUI下载, 大家比较一下..] 2.还有JPEG图版支持 3.ListView控件支持. 4.Menu菜单支持. 5.ScrollBar滚动条支持. 6.multi-ControlLER多控制器支持.

    标签: UCGUI MemDev 3.90 3.24

    上传时间: 2017-03-18

    上传用户:zhanditian

  • The TW2835 has four high quality NTSC/PAL video decoders, dual color display ControlLERs and dual v

    The TW2835 has four high quality NTSC/PAL video decoders, dual color display ControlLERs and dual video encoders. The TW2835 contains four built-in analog anti-aliasing filters, four 10bit Analog-to-Digital converters, and proprietary digital gain/clamp ControlLER, high quality Y/C separator to reduce cross-noise and high performance free scaler. Four built-in motion,

    标签: dual ControlLERs decoders display

    上传时间: 2017-03-20

    上传用户:来茴

  • 这是I2c网关Id独立烧写程序

    这是I2c网关Id独立烧写程序, 烧写的ID必须要求是:“0~9”、“a~z”、“A~Z”的16为字符才能烧写成功。 其中当是输入的小写字母时,自动转换为大些烧入。 如: 1) # ./burnID 0123456789abcdef 烧入的是:0123456789ABCDEF 2] # ./burnID 0123456789@ cdef 烧入不成功,因为有其他字符 3) # ./burnID 0123456789abcdefDfs 烧入也不成,因为超过16个字符 built-in analog anti-aliasing filters, four 10bit Analog-to-Digital converters, and proprietary digital gain/clamp ControlLER, high quality Y/C separator to reduce cross-noise and high performance free scaler. Four built-in motion,

    标签: I2c 网关 独立 烧写程序

    上传时间: 2017-03-20

    上传用户:playboys0