The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上传时间: 2013-11-03
上传用户:1037540470
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间: 2014-11-26
上传用户:erkuizhang
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间: 2013-10-22
上传用户:aeiouetla
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上传时间: 2013-12-07
上传用户:bruce
本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟,突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点,并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后,可应用于实际的数字钟显示中。 关键词:Verilog HDL;硬件描述语言;FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL;hardware description language;FPGA
上传时间: 2013-11-10
上传用户:hz07104032
a8259 可编程中断控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上传时间: 2015-01-02
上传用户:panpanpan
电机motor power 公司
上传时间: 2013-10-18
上传用户:qiaoyue
The power of programmability gives industrial automation designers a highly efficient, cost-effective alternative to traditional motor control units (MCUs)。 The parallel-processing power, fast computational speeds, and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control (FOC)。 Additionally, Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing (DSP) that can tackle compute-intensive functions such as PID Controller, Clark/Park transforms, and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving, proven, motor-control reference designs. The kit also shortens the process of developing custom control capabilities, with integrated peripheral functions (Ethernet, PowerLink, and PCI® Express), a motor-control FPGA mezzanine card (FMC) with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators, and prototyping support for evaluating alternative front-end circuitry.
上传时间: 2013-10-28
上传用户:wujijunshi
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上传时间: 2013-11-06
上传用户:WMC_geophy
Abstract: This application note explains how to design an intelligent lighting controller that senses and measures the ambient lightlevel with an ambient light sensor (ALS). Equipped with a real-time clock (RTC), the controller also knows when to turn lighting on oroff at specified times. The system presented in this document can be used to control all luminaires that are mains-supply operated.Controller software is also provided in hex format.
上传时间: 2013-11-18
上传用户:AbuGe