Abstract: Investment in smart meters and smart grid end equipment continues to grow worldwide as countriestry to make their electric delivery systems more efficient. However, as critical as the electric deliveryinfrastructure is, it is normally not secured and thus subject to attack. This article describes the concept oflife-CYCLE security—the idea that embedded equipment in the smart grid must have security designed into theentire life of the product, even back to the contract manufacturer. We also talk about how life-CYCLE securityapplies to embedded equipment in the smart grid. Potential threats are discussed, as are potential solutionsto mitigate the risks posed by those threats.
上传时间： 2014-12-24
上传用户：熊少锋
高的工作电压高达100V N双N沟道MOSFET同步驱动 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty CYCLEs with accurate CYCLE-by-CYCLE current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
上传时间： 2013-10-24
上传用户：wd450412225
Although recent popular attention is focused on LithiumIon batteries, one must not forget that other batterychemistries, such as Nickel Cadmium (NiCd) and NickelMetal Hydride (NiMH) have advantages in rechargeablepower systems. Nickel-based batteries are robust, capableof high discharge rates, have good CYCLE life, do notrequire special protection circuitry and are less expensivethan Li-Ion. Among the two, NiMH batteries are rapidlyreplacing NiCd because of their higher capacity (40% to50% more) and the environmental concerns of the toxiccadmium contained in NiCd batteries.
上传时间： 2013-11-04
上传用户：qq10538412
IC 特色 : ˙ 半谐振模式之 ZVS零电压切换 , 能有效降低切换损失 , 提高效率 , 并具展频功能 , 改善EMI . ˙ 轻 / 重载的 Duty Factor 皆在 CCM 与 DCM 边缘 , 是最能发挥次级 "同步整流" 效率的一种工作模式 . ˙ 空载时进入 CYCLE Skipping ( Typical 0.3W ) , 有效达成环保规範 . ˙ 内建 "LEB前缘遮没" 功能 , 避免电流迴授失真 . ˙ 能随输入电压变化 , 自动补偿 OPP过功率保护点 . ˙ 精密的 OVP 过压保护点可自行设定 . ˙ 完整的保护功能 : OVP过压保护 , OCP过流保护 , OPP过载保护 , SWP线圈短路保护 , SCP输出短路保护 , OTP过温度保护 .
上传时间： 2014-12-24
上传用户：回电话#
实时时钟是微机保护装置的重要部件，在讨论PCF8583结构与功能的基础上，提出采用dsPIC33F系列微处理器与串行I2C时钟PCF8583的接口设计方案，给出了相应的接口电路与软件流程。该设计方案结构简单，可靠性高，开发周期短，具有一定的实用与参考价值。所设计的微机保护装置已投入现场运行，效果良好。 Abstract: Real-time clock chip is an important part in microcomputer protection device.Based on discussing the structure and function of PCF8583，a new interface scheme which uses dsPIC33F microprocessor and serial clock chip（I2C）PCF8583is proposed.The method of the circuit design and the main software flow are introduced in this paper.The scheme has simple structure，higher reliability and shorter exploitation CYCLE，so has definite practicality or reference value.The microcomputer protection device has been put into operation with better effects.
上传时间： 2013-11-18
上传用户：Thuan
数字信号处理器dsPIC33F集多通道高精度A/D转换、多通讯模式、看门狗、CMOS Flash技术等于一体，其内部可完成所有数据操作，实现总线不出芯片技术。将该处理器应用于微机保护装置，提出基于dsPIC33F微处理器的微机保护装置的设计方案，给出相应的接口电路与软件流程。该设计方案结构简单，性价比及可靠性高，开发周期短，具有一定的实用推广价值。所研制的微机保护装置现场运行效果良好。 Abstract: The dsPIC33F microprocessor has a plentiful interior resource which contains multi-channel，high precision A/D converters，multi-communication module，watchdog，CMOS Flash technology，and so on.All data manipulations is accomplished interiorly.What is more，it makes the technology that bus does not go beyond the chip comes into practice.The paper put forwards a design scheme based on dsPIC33F microprocessor.The scheme has the advantages of simple structure，high reliability and shortened exploitation CYCLE.What is more，it has definite practicality and reference.The microcomputer protection device has been put into operation with excellent effects.
上传时间： 2013-11-16
上传用户：开怀常笑
介绍了用单片机C 语言实现无功补偿中电容组循环投切的基本原理和算法，并举例说明。关键词：循环投切;C51;无功补偿中图分类号： TM76 文献标识码： BAbstract: This paper introduces the aplication of C51 in the controlling of capacitorsuits CYCLE powered to be on and off in reactive compensation.it illustrate thefondamental principle and algorithm with example.Key words: CYCLE powered to be on and off; C51; reactive compensation 为提高功率因数，往往采用补偿电容的方法来实现。而电容器的容量是由实时功率因数与标准值进行比较来决定的，实时功率因数小于标准值时，需投入电容组，实时功率因数大于标准值时，则需切除电容组。投切方式的不合理，会对电容器造成损坏，现有的控制器多采用“顺序投切”方式，在这种投切方式下排序在前的电容器组，先投后切；而后面的却后投先切。这不仅使处于前面的电容组经常处于运行状态，积累热量不易散失，影响其使用寿命，而且使后面的投切开关经常动作，同样减少寿命。合理的投切方式应为“循环投切”。这种投切方式使先投入的运行的电容组先退出，后投的后切除，从而使各组电容及投切开关使用机率均等，降低了电容组的平均运行温度，减少了投切开关的动作次数，延长了其使用寿命。
上传时间： 2014-12-27
上传用户：hopy
The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write CYCLE with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self−timed write CYCLE. Additionally, the CAT28LV64 features hardware and software write protection.
上传时间： 2013-11-16
上传用户：浩子GG
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock CYCLE of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock CYCLE of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
