本实验要求设计一个简易的频率计，实现对标准的方波信号进行频率测量，并把测量的结果送到8 位的数码管显示，所要求测量范围是1Hz~99999999Hz。整个设计的基本原理就是对1 秒钟之内输入的方波进行计数，把所得数据保存在计数器里，经过译码器处理之后，然后送往数码管显示。这里采用的方案是在采样时钟的上升沿开始计数，然后在下一个上升沿把计数器里的数据送往数码管，并且把计数器清零，让其重新计数。整个方案的实现主要分为四个模块：时钟分频(clk_div)模块、计数器模块(counter)、译码器模块(seg8)、扫描输出(saomiao)模块
标签： 频率计设
上传时间： 2013-11-20
上传用户：avensy
#include <at24c01a.h>/*************************************************向24C01A写入一个字节输入：E2ROM地址，字节数据******************************************************/void write24c01a(uchar uadd_1,uchar udata_1){sendbyte=0xa0;start();send(sendbyte);if (!ack())continue;send(uadd_1);if (!ack())continue;send(udata_1)if (!ack())continue;stop();}/**********************************发送开始*****************************************/void start(void){a_scl=1;a_sda=1;a_sda=0;a_scl=0;a_scl=1;}/********************************************发送停止*******************************************/void stop(void){a_scl=0;a_sda=0;a_scl=1;a_sda=1;} /*********************************************发送反馈************************************************/bit ack(void){int a_acka_scl=0;a_scl=0;a_scl=0;a_scl=1;a_ack=a_sda;a_scl=0;return(a_ack)}/**************************************发送无反馈********************************************/bit noack(void){int a_ack;a_scl=1;a_scl=1;a_scl=0;}/*******************************************发送****************************************************/void send(uchar undata){uchar i;sendbyte=undatafor(i=8;i>0;i--){a_sda=sendbyte7;a_scl=0;a_scl=1;sendbyte=sendbyte<<1}}/********************************************接受****************************************************/ void receive(void){int i;uchar data;for(i=8;i>0;i--){ a_scl=1;receivebyte7=a_sda;a_scl=0;receivebyte=receivebyte>>1}receivedata=receivebyte;}/********************************************向 24c01a读一个字节；输入：EEROM地址；输出：EEROM数据；********************************************/void read24c01a(uchar counter){receivebyte=0xa1;start();send(receivebyte);if (!ack())continue;send(counter);if (!ack())continue;receive()noack();stop();}
上传时间： 2013-12-23
上传用户：wxhwjf
单片机系统“PC”失控的软件措施Software Measure of GettingO uto fC ontrolfo r“PC"in S ingleC hipC omputerS ystem谧 加 春 王 晓 基 雷 小 华(江 西 理 工 大 学机 电 工 程 学 院 ，赣 州 34 10 00)摘要单片机系统在实际工业现场中可能遇到各种干扰和自身的随机性故障。现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针“PC”失控就是常见的故障之一，如果发生“PC”失控，将导致CPI工作混乱，酿成严重的事故。研究了“PC”失控的原因，并指出软件抗干扰的几种方法，有效保证单片机系统的正常工作。关键词单片机“PC”失控抗干扰Abstract Inp racticalin dustrialfi elds,th ereis v ariousin terferencea fectingo perationo fsi nglec hipc omputersy stemsa ndt hec omputersy stems。fac吨random faults饰themselves. It is very common that the severe environment makes the computer systems abnormal. The program counter "PC"gettingo utof co ntorlis on eo fth ec ommonfa ults.If th isoc curs,C PUw ouldb eru nningo utof or deran din torducesse riousan cient.T hec ausesof " PC"geting out of control， studied in this paper and some countermeasures of anti-interference师software are given to ensure single chip computer systemworking properly.Keywords Single。饰computer Porgramc ounter"P C" Anti-interfeernc 在设 计 和 开发单片机系统时，一般难以周全地预计单片机系统在实际工业现场中可能遇到的各种干扰和自身的随机性故障。因此，除了采取防止和抑制干扰的各项措施外，还应该借助于软件措施克服某些干扰，系统还应具备迅速自行恢复的能力。本文介绍的应对单片机系统PC失控的软件措施，设计灵活，节省硬件资源，能保证测控系统长期可靠地运行。MC S- 5 1单片机以其优良的性能价格比大量应用于工业现场测试和控制领域。但是，现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针PC失控就是常见的故障之一，一旦发生PC“走飞”，计算机系统就会出现工作混乱，酿成严重的事故。为 了 在 CP 失控时尽量减少由此带来的不利影响，并尽快使系统恢复正常，需要采取一定的软件措施和硬件措施。常见的硬件措施有“看门狗”电路。软件措施设置的前提条件是:①在干扰作用下，微机系统硬件部分不会受到任何损坏，或者损坏部分设置有监测状态可供查询;②程序区不会受到干扰侵害。单片机系统的程序和表格以及重要的参数均设置在ROM区，不会因干扰的侵人而改变;③ RAM区中的重要数据不会被破坏，或者虽然被破坏，但是可以重新建立。
上传时间： 2013-11-02
上传用户：bhqrd30
针对UHF读写器设计中，在符合EPC Gen2标准的情况下，对标签返回的高速数据进行正确解码以达到正确读取标签的要求，提出了一种新的在ARM平台下采用边沿捕获统计定时器数判断数据的方法，并对FM0编码进行解码。与传统的使用定时器定时采样高低电平的FM0解码方法相比，该解码方法可以减少定时器定时误差累积的影响；可以将捕获定时器数中断与数据判断解码相对分隔开，使得中断对解码影响很小，实现捕获与解码的同步。通过实验表明，这种方法提高了解码的效率，在160 Kb/s的接收速度下，读取一张标签的时间约为30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
上传时间： 2013-11-10
上传用户：liufei
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter;
上传时间： 2013-10-30
上传用户：wqxstar
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上传时间： 2013-11-11
上传用户：gundamwzc
This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
标签： register straightforward universal storage
上传时间： 2013-12-28
上传用户：努力努力再努力
这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可
上传时间： 2015-08-06
上传用户：我们的船长
Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
标签： Spartan drives This perphrials
上传时间： 2014-05-29
上传用户：SimonQQ
This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED
标签： description provides transfer example
上传时间： 2016-04-24
上传用户：ecooo
