// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
标签： Description Behavorial wb_master Filename
上传时间： 2014-07-11
上传用户：zhanditian
This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for algorithms listed in the textbook Global Positioning Systems, Inertial Navigation, and Integration, by M. S. Grewal, Lawrence Weill, and A. P. Andrews, published by John Wiley and Sons, 2000. Contents: MATLAB (Version 5.2) Demonstrations & Scripts Chapter4 ephemeris.m calculates the GPS satellite position in ECEF coordinates from its ephemeris parameters. Chapter5 Klobuchar_fix.m calculates the ionospheric delay. Chapter6 (shows the quaternion utilities)
标签： demonstration diskette contains programs
上传时间： 2016-10-20
上传用户：坏天使kk
个人所得税计算器 v个人所得税计算器
标签： 计算器
上传时间： 2014-01-23
上传用户：bibirnovis
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
代码分为两部分：ff_const_mul.v和ff_mul.v，从而实现GF乘法器，VERILOG编写
标签： ff_const_mul ff_mul 分 代码
上传时间： 2016-11-13
上传用户：
内核参数传递 此参数指明包含引导扇区的设备名（如：/dev/had），若此项忽略，则从当前的根分区中读取引导扇区。
上传时间： 2016-11-15
上传用户：磊子226
Marvell WLAN Firmware Specification v5.1 PDF from libertas-dev ML
标签： Specification libertas-dev Firmware Marvell
上传时间： 2013-12-13
上传用户：三人用菜
牛顿迭代法 若高阶非线性方程组: u ( x , y) = 0 v ( x , y) = 0 可以用迭代公式
上传时间： 2014-02-10
上传用户：wl9454
ram_dp_ar_aw.v 应该蛮有用的
标签： ram_dp_ar_aw
上传时间： 2013-12-03
上传用户：cxl274287265
