一共有三种方式来发送和接收SMS信息：Block Mode, Text Mode和PDU Mode。其中PDU Mode被所有手机支持，可以使用任何字符集，这也是手机默认的编码方式。其中又分7bit-160，8bit-140，16bit-70的方式，我们中文用16bit70的方式。
上传时间： 2014-12-06
上传用户：bakdesec
Linux那些事儿之我是Block层，对于block层的一些通俗解释
标签： linux
上传时间： 2015-12-06
上传用户：qiubingfu
在深入了解Flash存储器的基础上，采用单片机自动检测存储器无效块。主要通过读取每一块的第1、第2页内容，判断该块的好坏，并给出具体的实现过程，以及部分关键的电路原理图和C语言程序代码。该设计最终实现单片机自动检测Flash坏块的功能，并通过读取ID号检测Flash的性能，同时该设计能够存储和读取1GB数据。 Abstract: On the basis of in-depth understanding the Flash chips，this paper designs a new program which using the SCM to detect the invalid block.Mainly through reading the data of the first and second page to detect the invalid block.Specific implementation procedure was given,and the key circuit schematic diagram and C language program code was introduced.This design achieved the function of using the MCU checks the invalid block finally，and increased the function by reading the ID number of Flash to get the performance of the memory.And the design also can write and read1GB data
上传时间： 2013-10-25
上传用户：taozhihua1314
介绍了电力操作电源与智能电池巡检系统的特点，给出了一种基于超低功耗单片机MSP430 F149针对中小型变电站自动化运行的专用设备的基本设计原理及实现方法，最后给出了详细硬件构成和软件实现。该系统能满足中小型变电站安全、可靠、自动运行的要求，并通过与上位机的串行通信实现变电站的远程管理和控制。 Abstract: The characters of the intelligent battery data logging system of the electric operation power are introduced.The basic design principle and the implemented methods of the special equipment which only designed for the middle or small transformer substation based on MSP430F149 are prescribed. Finally, the hardware block diagram and the software flow chart are also given. The function that the system finally needs to realize can basically meet with the middle or small transformer substation’s satisfy, reliably,and automatic running.And it can also realize the transformer substation long-distance management and control by serial communicating with the host computer.
上传时间： 2013-11-25
上传用户：黄华强
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are orientedin the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic inputand output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, andprevent noise currents on a data bus or other circuits from entering the local ground and interfering with ordamaging sensitive circuitry.
上传时间： 2013-10-24
上传用户：hbsunhui
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
This an adaptive receiver for a direct-sequence spread spectrum (DS-SS) system over an AWGN channel. The adaptive receiver block is modified from the LMS adaptive filter block in DSP Blockset. For DS-SS signal reception, the adaptive filter needs to have multi-rate operation. The input sample rate is equal to chip rate and the output is at symbol rate. Two rates are related by PG, processing gain
标签： direct-sequence adaptive receiver spectrum
上传时间： 2014-01-16
上传用户：D&L37
IDEA v2.2 IDEA encryption for dos. IDEA stands for International Data Encryption Algorithm it was invented by Xuejia Lai and James Massey in Switzerland its a private key block algorithm, and is thought to be very secure.
标签： IDEA International Encryption encryption
上传时间： 2013-12-18
上传用户：gxf2016
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
标签： Description Behavorial wb_master Filename
上传时间： 2014-07-11
上传用户：zhanditian
