Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.
标签： Avalon_VGA
上传时间： 2015-07-07
上传用户：kikye
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model
标签： Algorithm Decoder DVB-RCS Release
上传时间： 2015-07-10
上传用户：清风冷雨
Turbo C - (C) Copyright 1987, 1988 by Borland International */ #define S_IREAD 0x0100 /* from SYS\STAT.H */ #define S_IWRITE 0x0080 /* from SYS\STAT.H */ #define TRUE 1 #define FALSE 0 #define MSGHEADER "MICROCALC - A Turbo C Demonstration Program" #define MSGKEYPRESS "Press any key to continue." #define MSGCOMMAND "Press / for the list of commands" #define MSGMEMORY "Memory Available:" #define MSGERROR "ERROR" 部分说明 #define MSGLOMEM "Not enough memory to allocate cell." #define MSGEMPTY "Empty" #define MSGTEXT "Text"
标签： International Copyright Borland S_IREAD
上传时间： 2013-12-26
上传用户：llandlu
#define MSGHEADER "MICROCALC - A Turbo C Demonstration Program" #define MSGKEYPRESS "Press any key to continue." #define MSGCOMMAND "Press / for the list of commands" #define MSGMEMORY "Memory Available:" #define MSGERROR "ERROR" #define MSGLOMEM "Not enough memory to allocate cell."
标签： define Demonstration MSGKEYPRESS MSGHEADER
上传时间： 2015-07-22
上传用户：xinzhch
Blind Equalizer 的演算法主要是利用CMA及 LMS 的配合，当CMA将EYE打开，使讯号趋近于正确值，就切换到LMS，利用Slicer的输出当作training sequence来调整Equalizer的系数，而Carrier Recovery 的部份，则是将phase error track出来
上传时间： 2013-12-28
上传用户：it男一枚
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
串口通讯使用说明 在两台机器运行serealcom.exe， 但必须保证用串口线连接， 选择串口时如出现error, 表明此串口正被其它设备使用。
上传时间： 2014-10-12
上传用户：洛木卓
// // BEZIER.RC2 - resources Microsoft Visual C++ does not edit directly // #ifdef APSTUDIO_INVOKED #error this file is not editable by Microsoft Visual C++ #endif //APSTUDIO_INVOKED
标签： APSTUDIO_INV Microsoft resources directly
上传时间： 2015-08-05
上传用户：han_zh
查找线性表中的某元素：L为带头接点的单链表的头指针，当第i个元素存在的时候，其值赋给e并返回OK,否则返回ERROR */
上传时间： 2013-12-14
上传用户：363186
The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time delay.
标签： autocorrelation objective generator projectis
上传时间： 2015-08-17
上传用户：ikemada
