·详细说明：Goertzel算法是DTMF信号检测的核心，它利用二极点的IIR滤波器计算离散傅立叶变换值，快速有效的提取输入信号的频谱信息。-Goertzel algorithm is the DTMF signal examination core, it uses two extremes the IIR filter computations to Be separated Fourier t
上传时间： 2013-04-24
上传用户：moshushi0009
·详细说明：用于语音识别，基于HMM模型，用C++语言编写。可用连续语音识别-It is based on HMM Model and developed with C++ which could Be used to continuous speech recognition.
上传时间： 2013-05-15
上传用户：凤临西北
·详细说明：GSM的编解码C源码(使用Intel的IPP包)堪称效率最高。-GSM arranges decodes the c source code (to use intel the ipp package) to may Be called the efficiency to Be highest文件列表: GSMAMR ......\api ...
上传时间： 2013-07-31
上传用户：exxxds
·详细说明：MPEG4实现的软件代码，极具参考价值-code of software to implement mpeg4, valuable to Be refrenced 文件列表: mpeg-4 tts ..........\source ..........\......\AboutDlg.cpp ..........\...
上传时间： 2013-04-24
上传用户：guanliya
This is a document for CYCLONE Develop Kits type LJ-FN300 FPGANIOS. Wish this would help you to find what kits can Be select to use.
标签： FPGANIOS document CYCLONE Develop
上传时间： 2013-08-16
上传用户：563686540
In this paper, we discuss efficient coding and design styles using verilog. This can Beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing Behavioral models. All theseproblems are accompanied by an example to have a Better idea, and these can Be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is Beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can Be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has Been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have Been largely disregarded. Under theSHARP TIREP project, an attempt has Been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily Be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should Be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上传时间： 2013-10-17
上传用户：tb_6877751
Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures， follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training evaluation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process， it can not only Be used in teaching， but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.
上传时间： 2013-11-19
上传用户：3294322651
Abstract: This application note descriBes how to design boost converters using the MAX17597 peakcurrent-mode controller. Boost converters can Be operated in discontinuous conduction mode (DCM) orcontinuous conduction mode (CCM). This operating mode can affect the component choices, stress levelin power devices, and controller design. Formulas for calculating component values and ratingsare alsopresented.
上传时间： 2013-11-16
上传用户：zcs023047
