SOME Background ON DESIGN PATTERNS The term “design patterns” sounds a bit formal to the uninitiated and can be somewhat off-putting when you first encounter it. But, in fact, design patterns are just convenient ways of reusing object-oriented code between projects and between programmers. The idea behind design patterns is simple-- write down and catalog common interactions between objects that programmers have frequently found useful.
标签: Background uninitiate PATTERNS patterns
上传时间: 2013-12-22
上传用户:shizhanincc
The book presents a historical Background of past and present guided missile systems and the evolution of modern weapons,discusses the generalized missile equations of motion, aerodynamic forces and coefficients, the important subject of the various types of tactical guidance laws and/or techniques, weapon delivery systems and techniques,strategic missiles and cruise missile theory and design.
标签: Background historical and presents
上传时间: 2017-08-14
上传用户:jennyzai
to subtract Background
标签: Background subtract to
上传时间: 2014-11-28
上传用户:225588
This m-file implements the frame difference algorithm for Background subtraction.
标签: subtraction implements difference Background
上传时间: 2013-12-26
上传用户:123456wh
在国内Protel软件一直大受欢迎,从DOS时代的Protel3.3(Autotrax 1.61)到现在具有EDA Client/Server (客户/服务器)即C/S“框架”体系结构的Protel98,它始终是PCB设计和制造领域的大众化工具软件,成为电子设计工作者们的首选。 在规范化的设计管理中,设计文件图样必须遵守相应的国家标准,如《电子产品图样绘制规则》、《设计文件管理制图》和《印制板制图》等,而由于Protel软件都是英文版,因此无法直接打印出符合国家标准的图纸,要将图纸规范化常用的方式是套打,即先将符合国家标准的表和汉字等打在纸上,再将该纸放入打印机,用Protel软件将印制板图打印其上,形成符合标准的文件,但这种做法效率很低,而且图形常会打偏,有时甚至会打反,经笔者试验,找到了一种简便的方法,使印制板图转换为AUTOCAD格式,再在AUTOCAD里一次性打印出符合标准的图纸。
上传时间: 2013-10-12
上传用户:Wwill
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth Background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
标签: Synthesis Machine Coding Styles
上传时间: 2013-10-15
上传用户:dancnc
本文详细讨论了VHDL语句对PLD设计的影响和设计经验,经典文章,值得仔细阅读消化。,PLD Programming Using VHDL
标签: Programming Using VHDL PLD
上传时间: 2013-11-17
上传用户:teddysha
本文简单讨论并总结了VHDL、Verilog,System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签: Verilog verilog System VHDL
上传时间: 2013-10-16
上传用户:牛布牛
本文讨论了如何设计有效的testbench,适合刚接触testbench不久的用户阅读提高 (xilinx公司编写)
标签: Testbenches Efficient Writing
上传时间: 2013-10-18
上传用户:xiaodu1124
这篇文章讨论了不同HDL代码的编写方式,对综合结果的影响。阅读本文对深入了解综合工具和提高HDL的编写水平有不少帮助,原文时针对Synopsys的综合软件论述的,但对所有综合软件,都有普遍的借鉴意义
标签: Synthesis Coding Styles Guide
上传时间: 2014-12-23
上传用户:huql11633