展讯PCB_Layout教程
标签： PCB_Layout 展讯 教程
上传时间： 2013-11-11
上传用户：tianyi223
各种常用的封装尺寸
标签： 封装尺寸
上传时间： 2013-11-20
上传用户：fhzm5658
在软件无线电数字接收机中，从AD前端采集过来的数字信号频率高达72 MHz，如此高的频率使得后端DSP不能直接完成相关的数字信号处理任务。因此合理的设计基于FPGA的DDC，以降低数字信号频率，方便后端DSP实时完成相关的数字信号处理任务就显得尤为重要。在很多数字信号处理系统中，数字信号频率是非常高的，而后端数字信号处理器件几乎不能满足系统的实时性要求，此时通过合理的设计DDC就可以解决上述问题。
上传时间： 2013-11-20
上传用户：520
开关电源的朋友注意啦
上传时间： 2013-11-20
上传用户：simonpeng
PCB布线的常见规则
上传时间： 2013-11-20
上传用户：nem567397
Altium Designer教程交互式布线篇
上传时间： 2013-11-01
上传用户：gxrui1991
protel使用的个问题和解答
标签： protel
上传时间： 2013-11-20
上传用户：z1191176801
PCB板材
上传时间： 2013-10-28
上传用户：Wwill
挠性印制板很容易在大应力的作用下造成开裂或断裂，在设计时常在拐角处采用抗撕裂结构设计以更好地改善FPC的抗撕裂的性能。
上传时间： 2013-11-20
上传用户：kelimu
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2013-11-20
上传用户：pzw421125
